Patents by Inventor Robert Campbell Aitken

Robert Campbell Aitken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180277211
    Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in write cycles by controlling a current and a voltage applied to terminals of the non-volatile memory device.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: Azeez Bhavnagarwala, Robert Campbell Aitken
  • Patent number: 10083748
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 25, 2018
    Assignee: ARM Ltd.
    Inventors: Robert Campbell Aitken, Lucian Shifren
  • Publication number: 20180254084
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Application
    Filed: April 30, 2018
    Publication date: September 6, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • Patent number: 10049735
    Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: August 14, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Bhavnagarwala, Robert Campbell Aitken, Lucian Shifren
  • Patent number: 10043559
    Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 7, 2018
    Assignee: ARM Ltd.
    Inventors: Bal S. Sandhu, Cezary Pietrzyk, Robert Campbell Aitken, George McNeil Lattimore
  • Patent number: 10032487
    Abstract: An apparatus including a Correlated Electron Switch (CES) element and a programing circuit is provided. The programing circuit provides a programing signal to the CES element to program the CES element to an impedance state of multiple impedance states when a number of times the CES element has been programed is less than a threshold.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 24, 2018
    Assignee: ARM Ltd.
    Inventors: Lucian Shifren, Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu
  • Patent number: 10008263
    Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in write cycles by controlling a current and a voltage applied to terminals of the non-volatile memory device.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 26, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Bhavnagarwala, Robert Campbell Aitken
  • Patent number: 9990992
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: June 5, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • Patent number: 9966138
    Abstract: According to an embodiment of the present disclosure, a device and a method are provided. The device includes one or more resistive random access memory (ReRAM) elements. The device further includes a random number generator configured to generate a random number in dependence on impedance values of the one or more ReRAM elements.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 8, 2018
    Assignee: ARM Ltd.
    Inventors: Lucian Shifren, Robert Campbell Aitken
  • Publication number: 20180114574
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Application
    Filed: October 25, 2016
    Publication date: April 26, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • Patent number: 9929149
    Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: March 27, 2018
    Assignee: ARM Limited
    Inventors: Saurabh Pijuskumar Sinha, Robert Campbell Aitken, Brian Tracy Cline, Gregory Munson Yeric, Kyungwook Chang
  • Publication number: 20180081384
    Abstract: Subject matter disclosed herein may relate to generation of programmable voltage references.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 22, 2018
    Inventors: Bal S. Sandhu, George McNeil Lattimore, Robert Campbell Aitken
  • Publication number: 20180026625
    Abstract: Subject matter disclosed herein may relate to programmable current for correlated electron switches.
    Type: Application
    Filed: July 25, 2017
    Publication date: January 25, 2018
    Inventors: Bal S. Sandhu, George McNeil Lattimore, Robert Campbell Aitken
  • Publication number: 20180012639
    Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.
    Type: Application
    Filed: September 5, 2017
    Publication date: January 11, 2018
    Inventors: Bal S. Sandhu, Cezary Pietrzyk, Robert Campbell Aitken, George McNeil Lattimore
  • Publication number: 20180012658
    Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.
    Type: Application
    Filed: September 20, 2017
    Publication date: January 11, 2018
    Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers
  • Publication number: 20170372783
    Abstract: According to an embodiment of the present disclosure, a device and a method are provided. The device includes one or more resistive random access memory (ReRAM) elements. The device further includes a random number generator configured to generate a random number in dependence on impedance values of the one or more ReRAM elements.
    Type: Application
    Filed: July 13, 2017
    Publication date: December 28, 2017
    Inventors: Lucian Shifren, Robert Campbell Aitken
  • Patent number: 9851738
    Abstract: Subject matter disclosed herein may relate to generation of programmable voltage references.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: December 26, 2017
    Assignee: ARM Ltd.
    Inventors: Bal S. Sandhu, George McNeil Lattimore, Robert Campbell Aitken
  • Publication number: 20170365600
    Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.
    Type: Application
    Filed: June 21, 2016
    Publication date: December 21, 2017
    Inventors: Saurabh Pijuskumar Sinha, Robert Campbell Aitken, Brian Tracy Cline, Gregory Munson Yeric, Kyungwook Chang
  • Patent number: 9805777
    Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: October 31, 2017
    Assignee: ARM Ltd.
    Inventors: Bal S. Sandhu, Cezary Pietrzyk, Robert Campbell Aitken, George McNeil Lattimore
  • Patent number: 9786370
    Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: October 10, 2017
    Assignee: ARM Ltd.
    Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers