Patents by Inventor Robert Eric Fesler

Robert Eric Fesler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230253956
    Abstract: A transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Patent number: 11664785
    Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: May 30, 2023
    Assignee: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Publication number: 20220190811
    Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Applicant: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Patent number: 11290090
    Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: March 29, 2022
    Assignee: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Publication number: 20210257998
    Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Application
    Filed: December 15, 2020
    Publication date: August 19, 2021
    Applicant: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Patent number: 7659703
    Abstract: A circuit for providing an improved “feed forward” zero in a feedback loop such that the zero has a frequency dependent on the transconductance (gm) of a common gate transistor, and pole and zero separation that is dependent on a multiple of the gm. The circuit includes an error amplifier and a compensation circuit. The compensation circuit provides a first feedback current and a second feedback current. The error amplifier receives a reference signal and a feedback signal. The feedback signal is provided by summing the first feedback current and the second feedback current.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: February 9, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Robert Eric Fesler, Chunping Song
  • Patent number: 7360118
    Abstract: A system for verifying data in a shadow memory is provided that includes a main memory, a shadow memory, a shadow memory initializer, and a shadow memory verifier. The main memory is operable to store main data persistently. The shadow memory is operable to store shadow data temporarily. The shadow data comprises a copy of the main data. The shadow memory initializer is operable to detect an initialization event and to initialize the shadow memory based on the initialization event. The shadow memory verifier is operable to detect a verification event and to verify the shadow data based on the verification event.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: April 15, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Robert Eric Fesler
  • Patent number: 6806773
    Abstract: Voltage regulators use capacitors to compensate the voltage regulator and provide stable performance. Capacitors have an inherent equivalent series resistance (ESR) that changes over various operating conditions including signal frequency, operating temperature as well as others. An apparatus and method compensates for the low ESR of capacitors to increase the total equivalent series resistance of the capacitor. By providing an “on-chip” resistance between the capacitor and the circuit ground potential, minimum total ESR can be provided such that stable load regulation is achieved with capacitors that would otherwise be undesirable for such use. Increasing the value of the output capacitor's equivalent series resistance allows wider ranging values of capacitance to be used. The increased range of capacitance values allows capacitors of different material types to be used.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: October 19, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Aaron Grant Simmons, Robert Eric Fesler