Patents by Inventor Robert F. Pfeifer

Robert F. Pfeifer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200110374
    Abstract: A building management system of a building including one or more computer-readable storage media having instructions that cause the one or more processors to operate a wireless power transmitter to transmit wireless power to one or more first building devices located within a zone of the building. The instructions cause the one or more processors to receive an indication of a zone power mode for the zone and operate the wireless power transmitter to switch from transmitting the wireless power to the one or more first building devices to transmitting the wireless power to one or more second building devices located within the zone of the building, wherein the one or more second building devices are indicated by the zone power mode, wherein at least one building device of the one or more second building devices is a different building device than the one or more first building devices.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 9, 2020
    Inventors: Ryan A. Piaskowski, Joseph H. Klotz, Matthew J. Deloge, Matthew F. Malcolm, Robert H. Harland, Radu M. Dorneanu, Brian J. Pfeifer, Karl F. Reichenberger
  • Patent number: 4888801
    Abstract: A hierarchical key management system includes a number of secure terminals. These terminals provide secure access to a corresponding number of users. A user inserts a security activation device or key into the secure terminal to access a secure connection through the established communication network. A group of secure wireline terminals is connected to a key certification authority. There may be several groups of key certification authorities and corresponding secure terminal users. At the highest level, a key certification center authorizes secure communications by the key certification authorities. In turn, the key certification authorities authorize secure communications between the users. As a result, if one level of key management is compromised, other levels and users are not affected.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: December 19, 1989
    Assignee: Motorola, Inc.
    Inventors: Robert I. Foster, Robert F. Pfeifer, Thomas J. Mihm, Jr.
  • Patent number: 4534104
    Abstract: A process for fabricating volatile and nonvolatile field effect devices on a common semiconductor wafer, and a unique composite structure for a nonvolatile memory device fabricated according to the process. A distinct feature of the process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. In one form, the method commences with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The succeeding contact etch step is followed by a deposition of a poly I layer, a resistor forming implant and a patterned etch of the poly I layer. Thereafter, a first isolation oxide is grown, selective implants are performed to center the memory window, the memory area is etched, and the memory area is covered by a regrowth of a very thin memory oxide.
    Type: Grant
    Filed: February 26, 1982
    Date of Patent: August 13, 1985
    Assignee: NCR Corporation
    Inventors: Vinod K. Dham, Edward H. Honnigford, John K. Stewart, Jr., Robert F. Pfeifer, Murray L. Trudel
  • Patent number: 4516313
    Abstract: A unified process for fabricating CMOS and SNOS devices on a common wafer. The process provides for the formation of poly resistors and interconnects at multiple levels while eliminating residual silicon nitride from active devices excepting the nonvolatile SNOS type memory cells. Foremost, the process significantly reduces the number of masking operations while limiting the fabrication temperatures at stages after the formation of the memory device dielectric. In the preferred arrangement, the process prescribes the formation of p and n-wells, gate oxides over the wells, and a patterned conductive poly layer thereupon. By alternate photoresist masking, the source/drain regions in the respective wells are then doped to coincide with the corresponding poly layer patterns. Thereafter, the SNOS device operational characteristics are refined, a first isolation layer of silicon dioxide is grown, and the memory dielectric is sequentially formed.
    Type: Grant
    Filed: May 27, 1983
    Date of Patent: May 14, 1985
    Assignee: NCR Corporation
    Inventors: Raymond A. Turi, Robert F. Pfeifer
  • Patent number: 4422885
    Abstract: Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.
    Type: Grant
    Filed: December 18, 1981
    Date of Patent: December 27, 1983
    Assignee: NCR Corporation
    Inventors: Ronald W. Brower, Samuel Y. Chiao, Robert F. Pfeifer, Roberto Romano-Moran
  • Patent number: 4391650
    Abstract: Disclosed is a process for a CMOS integrated circuit having polysilicon conductors of a single conductivity, single impurity type. After forming the conductors they are covered by an oxidation and diffusion mask consisting of a dual layer of silicon dioxide and silicon nitride. Then, source and drains of the p-channel and n-channel transistors are formed. Next, an implantation or diffusion barrier is grown over sources and drains. The oxidation and diffusion mask over all the conductors is then removed and they are all doped simultaneously using a single type impurity.The process may be used to additionally form polysilicon resistors by initially doping the polysilicon to a low level of conductivity. After forming the conductors and resistors they are covered by the oxidation and diffusion mask. Then a resistor mask of either silicon nitride or polysilicon is formed over the resistors to protect them during the high conductivity doping of the conductors.
    Type: Grant
    Filed: December 22, 1980
    Date of Patent: July 5, 1983
    Assignee: NCR Corporation
    Inventors: Robert F. Pfeifer, Murray L. Trudel
  • Patent number: 4352952
    Abstract: A data security module for encrypting and decrypting computer data contains, in addition to the encryption logic, interface logic to allow direct memory access to a computer. The security module sits as a computer peripheral device and after being instructed as to the location and quantity of data by the computer, accesses the data directly from the computer memory without disturbing the processor to provide parallel encryption or decryption of computer memory data.
    Type: Grant
    Filed: March 3, 1980
    Date of Patent: October 5, 1982
    Assignee: Motorola Inc.
    Inventors: Charles A. Boone, Robert F. Pfeifer
  • Patent number: 4281216
    Abstract: In a data encryption/decryption system providing for security of data communications channels, a sub-system for generating, transporting encryption/decryption keys and for introducing those keys into the system while at the same time providing a high level of security for the keys and, hence, the encryption/decryption system.
    Type: Grant
    Filed: April 2, 1979
    Date of Patent: July 28, 1981
    Assignee: Motorola Inc.
    Inventors: Gerald J. Hogg, Robert A. Newman, Robert F. Pfeifer
  • Patent number: D255899
    Type: Grant
    Filed: June 8, 1978
    Date of Patent: July 15, 1980
    Assignee: Motorola, Inc.
    Inventors: Joseph W. Karas, Robert F. Pfeifer, Robert Samson
  • Patent number: D263395
    Type: Grant
    Filed: April 2, 1979
    Date of Patent: March 16, 1982
    Assignee: Motorola Inc.
    Inventors: Joseph W. Karas, Robert F. Pfeifer, Robert Samson
  • Patent number: D264843
    Type: Grant
    Filed: April 2, 1979
    Date of Patent: June 8, 1982
    Assignee: Motorola Inc.
    Inventors: Joseph W. Karas, Robert F. Pfeifer, Robert Samson