Abstract: This invention is a data processor including a data transfer controller. The data transfer controller includes internal and external memory interfaces coupled to internal and external memory, respectively. A pipeline controller controls the internal memory interface and the external memory interface. A source address generator generates addresses for reading data. A destination address generator generates addresses for writing data. Buffer circuitry interposed between the source address generator and the destination address generator permits data to be aligned to differing source and destination data word sizes and differing data word boundaries. An external sequencer provides control signals for the external memory via the external memory interface. In the preferred embodiment, the buffer circuitry includes a first-in-first-out (FIFO) buffer having a plurality of registers. This permits continued operations in many cases when either the source or destination memory operations temporarily stall.

Abstract: There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and an inter-processor communication link allows the processors to communicate with each other for the purpose of establishing operational modes. A parameter memory, accessible via the crossbar switch, is used in conjunction with the communication link for control purposes. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: An SLM-based digital display system (10) having a graphics display subsystem (13 and 18) for closed captioning, on-screen displays, and other graphics images that are overlaid on the video image. The graphics display subsystem (13 and 18) has a graphics processor (21) that prepares the graphics data, which is inserted into the video data path after video data processing and prior to a look-up table unit (27). A select logic unit (24) provides a control signal to a multiplexer (26) that selects between video data and graphics data for input to the look-up table unit (27). The look-up table unit (27) performs its mapping according to the type of data received, such as by linearizing video data or palletizing graphics data.

Abstract: A method for processing video data to produce a progressively scanned signal from an input of conventional interlaced video. The data is received at a processor (1), used to determine a motion signal (26) over time between field of the data. The motion signal is filtered to reduce errors caused by noise-corrupted video sources and then further filtered to spread out the determined motion signal. Edge information (30) is located and combined with the motion signal to produce an integrated progressive-scan signal (36) for display on a video display device, producing images with sharper edges and motion signals which have a lower susceptibility to noise.

Abstract: A method of encoding video display data, after that data has been previously converted from a film frame rate to a faster video frame rate, such as by 3:2 pulldown. The data is first re-converted to the film frame format, as progressive frames (21). This progressive frame data is processed to determine where scene cuts occur (22). The data is then encoded consistent with MPEG encoding techniques, but with the scene cut information being used to begin groups of pictures (GOPs) at scene cuts and to determine where intrapictures, predicted pictures, or interpolated pictures shall occur (23).

Abstract: A method and display system for reducing the visual impact of defects present in an image display. The display includes an array of pixels, each non-defective pixel being selectively operable in response to input data by addressing facilities between an "on" state, whereat light is directed onto a viewing surface, and an "off" state, whereat light is not directed onto the viewing surface. A defect is the result of a defective pixel which does not respond to the input data presented by the addressing facilities, typically by continuously remaining in its "on" or "off" state. Each defective pixel is immediately surrounded by a first ring of compensation pixels adjacent to the central defective pixel. The compensation pixels are immediately surrounded by a second ring of reference pixels spaced from the central defective pixel.

Abstract: A system (14') for processing pixel video data having a selectable number of bits is provided. The system (14') comprises first, second and third video processors (20), (22) and (24). The first video processor (20) receives and processes pixel data of a luminance video signal. The second video processor (22) may receive and process pixel data of a chrominance video signal and may generate one of first, second and third video signal outputs. The third video processor (24) may process the chrominance video signal and may also generate at least two of the output video signals.

Abstract: A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

Abstract: A method of implementing pulse-width modulated image display systems (10, 20) with a spatial light modulator (SLM) (15) configured for split-reset addressing. Display frame periods are divided into time slices. Each frame of data is divided into bit-planes, each bit-plane having one bit of data for each pixel element and representing a bit weight of the intensity value to be displayed by that pixel element. Each bit-plane has a display time corresponding to a number of time slices, with bit-planes of higher bit weights being displayed for more time slices. The bit-planes are further formatted into reset groups, each reset group corresponding to a reset group of the SLM (15). The display times for reset groups of more significant bits are segmented so that the data can be displayed in segments rather than for a continuous time. During loading, segments of corresponding bit-planes are temporally aligned from one reset group to the next.

Abstract: A data processor with a transparency detection data transfer controller transfers data from a block of source addresses to a block of destination addresses. A transparency register stores transparency data. A comparator compares the recalled data to the stored transparency data and indicates whether the data to be transferred is to be written to the memory. The recalled data to be transferred is not to be written into the memory if it matches the transparency data. The transparency register may store a multiple of a multibit minimum amount of data to be transferred. The data to be transferred has a selected size which is an integral multiple of a minimum amount of data to be transferred. The comparator includes plural data comparators corresponding to each multibit minimum amount of data to be transferred.

Abstract: A visual information system to capture an input image using a camera 22, manipulate the image using processor 28, and project the processed image using optics 33 to superimpose the processed image on the actual object being observed by a viewer. Processing is done in real-time to allow the viewer to see both the actual and processed images while the viewer moves and changes viewing angles. Areas of interest in the displayed image may be highlighted or include graphical information for the viewer.

Abstract: A multi-format display system including hardware and algorithms for digital and High Definition Television. The system includes a light source (120), a tuner/preprocessor unit (114), a processor unit (116), a spatial light modulator (118), and a display surface (128). The processor unit can scale and format the data for a number of standardized-format video broadcast signals, and can perform additional interpolation to eliminate artifacts.

Abstract: A digital television system (10) System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j).

Abstract: A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, dimension values defining a block of addresses, guide table having guide table entries and a table pointer. Each guide table entry has an address value. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of a block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table.

Abstract: There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories, are contained on a single silicon chip.

Abstract: A pixel generator and method of generating pixel data for creating frames of video pixel data from fields of input video pixel data. The pixel processor 16 includes a field buffer circuit 36 that stores a plurality of fields of input video pixel data. Coupled to the field buffer are a feature detector 38 and a pixel generator 40. The feature detector 38 generates one or more feature magnitude signals based upon one or more of the fields of input video pixel data. The pixel generator 40 has at least two logic circuits for generating at least two different intermediate pixel data values based on the input pixel data. Coupled to feature detector 38 is feature analyzer 42 that selects a feature weight corresponding to each intermediate pixel data value, the weight being based upon the value of the feature magnitude signals. Coupled to feature analyzer 42 and pixel generator 40, is a pixel averager 44 that generates output pixel data based upon a weighted average of the intermediate pixel data values.

Abstract: A sequential color system is provided in which a processor (22) is coupled to a memory (24) and a receiver (27). Images are generated by shining light from a light source (28) through a color wheel (30) and onto DMD array (26). Light from the DMD array (26) is shone on screen (32). By adjusting the speed and make-up of color wheel (30) color separation is greatly reduced or eliminated. Also there are techniques for sequential imaging which may be applied to other technologies, such as CRT technologies.

Abstract: An SLM-based video receiver (10) receives a video input on a field-by-field basis at a signal interface unit (11) and passes the input to a processor (12). The processor (12) performs analog-to-digital conversion if the pixel data is analog and also performs other enhancements to prepare the pixel data for loading into a video memory (14). Pixel data from the processor (12), representing a field of pixel data, is stored into the memory (14) for loading into rows of pixel elements of a spatial light modulator (16). The spatial light modulator (16) receives the pixel data in rows. The addressing functions of the spatial light modulator (16) are used to generate additional display rows of pixel data per field. Thus, the SLM-based video receiver (10) displays a video frame having more lines than the field of pixel data.

Abstract: A multi-processing system which handles image processing and graphics by constructing a crossbar switch capable of inter-connecting any processor with any memory in any configuration for the interchange of data. The system is capable of connecting n parallel processors to m memories where m is greater than n.

Abstract: A processing system operating on data words having first and second portions includes a memory bank comprising first and second memories each with associated first and second set of address inputs. First memory includes a first storage location storing the first portion of a first word accessible by a set of address bits received at the first inputs and a second set of address bits received at the second inputs. The first memory further includes a second storage location storing the second portion of a second word accessible by the first set of bits received at the first inputs and a third set of bits received at the second inputs. Second memory includes a first storage location storing the second portion of the second word accessible by the first set of bits received at the first inputs and the second set of bits received at the second inputs.