Patents by Inventor Robert J. Madge

Robert J. Madge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130154109
    Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, John W. Osenbach, Anwar Ali, Donald E. Hawk, Robert J. Madge
  • Patent number: 6782500
    Abstract: A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: August 24, 2004
    Assignee: LSI Logic Corporation
    Inventors: Robert J. Madge, Emery Sugasawara, W. Robert Daasch, James N. McNames, Daniel R. Bockelman, Kevin Cota
  • Patent number: 6598194
    Abstract: A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: July 22, 2003
    Assignee: LSI Logic Corporation
    Inventors: Robert J. Madge, Emery Sugasawara, W. Robert Daasch, James N. McNames, Daniel R. Bockelman, Kevin Cota