Patents by Inventor Robert J. Wojnarowski

Robert J. Wojnarowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5434751
    Abstract: A multichip module (incorporating a high density interconnect structure) has: a first portion containing a substrate with semiconductor chips therein, with each chip having contact pads; a second portion comprising a (HDI) structure interconnecting the chip pads; and a solvent-soluble release layer bonding the two portions together and allowing for easy removal of the HDI structure from the substrate of the module by immersion in an appropriate solvent for the release layer.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: July 18, 1995
    Assignee: Martin Marietta Corporation
    Inventors: Herbert S. Cole, Jr., Theresa A. Sitnik-Nieters, Robert J. Wojnarowski, John H. Lupinski
  • Patent number: 5422513
    Abstract: A high density interconnect (HDI) structure having a dielectric multi-layer interconnect structure on a substrate is fabricated by forming a chip well, placing a chip in the well, and connecting the chip to the interconnect structure. Additionally, temperature sensitive chips or devices may be located beneath the dielectric multi-layer interconnect structure. A spacer die may be located in the substrate while the interconnect structure is fabricated and removed after a chip well aligned with the spacer die is formed, in order to accommodate a chip thickness which is greater than the dielectric multi-layer interconnect structure thickness.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: June 6, 1995
    Assignee: Martin Marietta Corporation
    Inventors: Walter M. Marcinkiewicz, Raymond A. Fillion, Barry S. Whitmore, Robert J. Wojnarowski
  • Patent number: 5391516
    Abstract: Semiconductor device contact pads are enhanced by forming a metal plate over at least a portion of the contact pad. "Enhancement" includes repair such as by bridging a reinforcing pad area over probe damage, general reinforcement or enlargement of a contact pad, and placement of a protective buffer pad over a contact pad. These methods are applicable to any semiconductor device with contact pads on a surface thereof, such as entire wafers, individual dice, and multi-chip High Density Interconnect (HDI) modules. The pad enhancement plate is formed by applying a planarizing dielectric layer over the entire device (if not already formed in the initial stages of HDI processing), and an enhancement access via is then formed to expose a portion of the contact pad to be enhanced. The entire device is metallized, and metal not over the exposed portion of the contact pad is subsequently removed.
    Type: Grant
    Filed: October 10, 1991
    Date of Patent: February 21, 1995
    Assignee: Martin Marietta Corp.
    Inventors: Robert J. Wojnarowski, Bernard Gorowitz
  • Patent number: 5381445
    Abstract: A munitions cartridge transmitter capable of emitting an electromagnetic signal after discharge from a cartridge propelling device comprises a signal generator, an electromagnetic signal transmitter coupled to the generator, an antenna coupled to the transmitter, and a hollow cartridge for housing the generator, the transmitter, and the antenna. The transmitter is energized after discharge of the cartridge propelling device by a power source contained in the cartridge.
    Type: Grant
    Filed: May 3, 1993
    Date of Patent: January 10, 1995
    Assignee: General Electric Company
    Inventors: John E. Hershey, Menahem Lowy, Lionel M. Levinson, Amer A. Hassan, Richard L. Frey, Kenneth B. Welles, II, Michael Gdula, Robert J. Wojnarowski
  • Patent number: 5366906
    Abstract: In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: November 22, 1994
    Assignee: Martin Marietta Corporation
    Inventors: Robert J. Wojnarowski, Constantine A. Neugebauer, Wolfgang Daum, Bernard Gorowitz, Eric J. Wildi, Michael Gdula, Stanton E. Weaver, Jr., Anthony A. Immorlica, Jr.
  • Patent number: 5359496
    Abstract: A body is hermetically sealed by electroplating a hermetic layer over the exterior surface of the body. A hermetic high density interconnect structure is provided by forming a continuous metal layer over the outermost dielectric layer of the multilayer interconnect structure and by disposing that continuous metal layer in a hermetically sealing relation to the substrate of the high density interconnect structure. A variety of techniques may be used for providing electrical feedthroughs between the interior and exterior of the hermetic enclosure as may a pseudo-hermetic enclosure in those situations where true hermeticity is not required.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: October 25, 1994
    Assignee: General Electric Company
    Inventors: William P. Kornrumpf, Robert J. Wojnarowski, Charles W. Eichelberger
  • Patent number: 5357403
    Abstract: Mispositioning of chips in a high density interconnect structure is compensated for by including a layer having alignment conductor in the high density interconnect structure without requiring adaptation of the signal conductor metallization levels of the high density interconnect structure. One level, two levels or more of alignment conductor may be employed. The alignment levels of the high density interconnect structure are preferably a ground plane, and if two layers of alignment conductors are provided, a power plane.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: October 18, 1994
    Assignee: General Electric Company
    Inventors: Theodore R. Haller, Robert J. Wojnarowski
  • Patent number: 5355102
    Abstract: Active components of a microwave system are interconnected on a substrate by a dielectric-overlay, high-density-interconnect structure in a manner which provides close impedance matching, minimizes impedance discontinuities and substantially increases the yield of good circuits.
    Type: Grant
    Filed: April 14, 1992
    Date of Patent: October 11, 1994
    Assignee: General Electric Company
    Inventors: William P. Kornrumpf, Robert J. Wojnarowski, Charles W. Eichelberger
  • Patent number: 5353498
    Abstract: Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: October 11, 1994
    Assignee: General Electric Company
    Inventors: Raymond A. Fillion, Robert J. Wojnarowski, Michael Gdula, Herbert S. Cole, Eric J. Wildi, Wolfgang Daum
  • Patent number: 5353195
    Abstract: A multi-chip module includes a substrate supporting a plurality of chips. A dielectric layer which overlies the chips and the substrate has a connection surface and a substrate surface with metallization planes having plane openings patterned on each surface and vias aligned with predetermined pads on the chips and predetermined portions of the metallization plane of the substrate surface. An adhesive layer is situated between the substrate and the substrate surface of the dielectric layer, and a pattern of electrical conductors extends through the vias to interconnect selected chips and selected portions of the metallization planes. In a related design, the dielectric layer may be a board having chip openings and conductive through-connections aligned with predetermined portions of the metallization plane of the substrate surface.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: October 4, 1994
    Assignee: General Electric Company
    Inventors: Raymond A. Fillion, Robert J. Wojnarowski
  • Patent number: 5348607
    Abstract: A mixture for affixing dice to a substrate includes a thermoplastic polyimide, a solvent for the polyimide, and a solvent which does not dissolve the polyimide but adds thixotropicity to the mixture. The mixture is applied to the substrate, the dice are placed thereon, and the solvents are evaporated to bond the dice to the substrate. The bond is radiation hard and exhibits high shear pull strength. A poor solvent for the polyimide, sprayed over the dice and exposed portions of die attach material, causes some polyimide to precipitate out of solution in the exposed portions of die attach material to form a grid that extends between the dice and prevents the dice from "swimming together" during high temperature processing. In a solvent die-attachment method, the substrate is first coated with a mixture of die attach material, and the mixture is dried. Spraying a solvent over the die attach material causes the material to soften so that the dice applied thereto may adhere.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: September 20, 1994
    Assignee: General Electric Company
    Inventors: Robert J. Wojnarowski, Charles W. Eichelberger
  • Patent number: 5336928
    Abstract: A hermetically sealed electronic package particularly adapted for high density interconnect (HDI) electronic systems, employs a ceramic substrate as the package base. The substrate is provided with module contact pads. A barrier support frame on the module contact pads divides them into inner and outer portions. A plurality of electronic components, such as integrated circuit chips, are fastened to the substrate within the perimeter of the barrier support frame, and interconnections are provided between inner portions of the module contact pads and contact pads on the electronic components. A polymer barrier layer is deposited over the area enclosed by the barrier support frame as well as a portion of the frame itself, and is overlaid with a metal barrier layer. A protective solder layer is deposited on the metal barrier layer to bridge any voids in the metal barrier layer.
    Type: Grant
    Filed: September 18, 1992
    Date of Patent: August 9, 1994
    Assignee: General Electric Company
    Inventors: Constantine A. Neugebauer, deceased, Robert J. Wojnarowski
  • Patent number: 5331203
    Abstract: A high density interconnect structure is rendered suitable for the packaging of overlay sensitive chips by providing a cavity in the high density interconnect structure which spaces the sensitive surface of such chips from the overlying high density interconnect structure in a manner which prevents undesired interactions between the dielectric of the high density interconnect structure and the chip.
    Type: Grant
    Filed: October 25, 1993
    Date of Patent: July 19, 1994
    Assignee: General Electric Company
    Inventors: Robert J. Wojnarowski, Charles W. Eichelberger, William P. Kornrumpf
  • Patent number: 5324687
    Abstract: A method of thinning dice or integrated circuit chips used in producing lightweight packaged electronic systems, such as HDI circuits and systems produced therefrom provides for positioning dice in a die carrier layer that allows for easy separation from the dice after completion of the die thinning step. A holding layer is then attached to the die carrier layer for ease of attaching it to a material removal device, such as a lapping machine or an ultrasonic milling machine. A portion of the die carrier layer, along its exposed side, is then removed by the material removal device as a consequence of removal, by the material removal device, of an expendable portion of the dice positioned within the die carrier layer. The holding layer and the die carrier layer are then separated from the thinned dice by a conventional method, such as chemical etching, solvent soaking or induction heating.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: June 28, 1994
    Assignee: General Electric Company
    Inventor: Robert J. Wojnarowski
  • Patent number: 5302547
    Abstract: A differentiable ablation approach to patterning dielectrics which are not of the same absorbance uses an absorbant dielectric at a specified laser wavelength over a non-absorbant dielectric at that wavelength. The absorbant dielectric may be laser-patterned and become an integral mask enabling plasma etching of the underlying non-absorbant dielectric. If the patterning of the absorbant dielectric involves vias, polymer ridges formed around via surfaces during laser patterning may be removed at the same time the underlying non-absorbant dielectric is etched using a transparent, oxygen plasma resistant mask. Alternatively, an inert mask may be used instead of the absorbant dielectric to allow plasma etching of the non-absorbant dielectric.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: April 12, 1994
    Assignee: General Electric Company
    Inventors: Robert J. Wojnarowski, Herbert S. Cole, Richard J. Saia, Thomas B. Gorczyca, Ernest W. Balch
  • Patent number: 5258647
    Abstract: A high acceleration object includes an electronic system which is operable at accelerations in excess of 20,000 g. Connections between integrated circuit chips and other portions of the electronic system are provided by metallization patterns disposed on polymer dielectric layers which are self-supporting across gaps between components. A high density interconnect structure is disposed within the cavity of a hermetically sealed package.
    Type: Grant
    Filed: August 26, 1992
    Date of Patent: November 2, 1993
    Assignee: General Electric Company
    Inventors: Robert J. Wojnarowski, Charles W. Eichelberger
  • Patent number: 5241456
    Abstract: An improved high density interconnect structure may include electronic components mounted on both sides of its substrate or a substrate which is only as thick as the semiconductor chips which reduces the overall structure thickness to the thickness of the semiconductor chips plus the combined thickness of the high density interconnect structure's dielectric and conductive layers. In the two-sided structures, feedthroughs, which are preferably hermetic, provide connections between opposite sides of the substrate. Substrates of either of these types may be stacked to form a three-dimensional structure. Means for connecting between adjacent substrates are preferably incorporated within the boundaries of the stack rather than on the outside surface thereof.
    Type: Grant
    Filed: July 2, 1990
    Date of Patent: August 31, 1993
    Assignee: General Electric Company
    Inventors: Walter M. Marcinkiewicz, Charles W. Eichelberger, Robert J. Wojnarowski
  • Patent number: 5225023
    Abstract: A mixture for affixing dice to a substrate includes a thermoplastic polyimide, a solvent for the polyimide, and a solvent which does not dissolve the polyimide but adds thixotropicity to the mixture. The mixture is applied to the substrate, the dice are placed thereon, and the solvents are evaporated to bond the dice to the substrate. The bond is radiation hard and exhibits high shear pull strength. A poor solvent for the polyimide, sprayed over the dice and exposed portions of die attach material, causes some polyimide to precipitate out of solution in the exposed portions of die attach material to form a grid that extends between the dice and prevents the dice from "swimming together" during high temperature processing. In a solvent die-attachment method, the substrate is first coated with a mixture of die attach material, and the mixture is dried. Spraying a solvent over the die attach material causes the material to soften so that the dice applied thereto may adhere.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: July 6, 1993
    Assignee: General Electric Company
    Inventors: Robert J. Wojnarowski, Charles W. Eichelberger
  • Patent number: 5214655
    Abstract: A packaged electronics system, having respective portions each with respective input and output ports, and having interconnection busses between certain of these ports, is tested as follows. Each input port has a set of first transmission gates associated therewith for selectively disconnecting it during testing from the end of each interconnection bus connected bit during normal operation. Each input port has a second set of transmission gates associated therewith for selectively applying test vectors thereto during testing as provided in parallel form from a serially loaded shift register. Each output port connects to the input connections of a respective set of tristate drivers for selectively applying its output signals at relatively low source impedance to at least one interconnection bus connected from the output connections of that set of tristate drivers.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: May 25, 1993
    Assignee: General Electric Company
    Inventors: Charles W. Eichelberger, Kenneth B. Welles, II, Robert J. Wojnarowski
  • Patent number: 5200810
    Abstract: The functionality, versatility and connection and packing density of a high density interconnect structure is enhanced by mounting one or more components on top of the high density interconnect structure for connection to conductors of the high density interconnect structure and the chips embedded within the high density interconnect structure. Both active and passive components may be mounted in this manner, as may components which would be adversely affected by high density interconnect structure fabrication temperatures or by the presence of the high density interconnect structure dielectric.
    Type: Grant
    Filed: April 5, 1990
    Date of Patent: April 6, 1993
    Assignee: General Electric Company
    Inventors: Robert J. Wojnarowski, Charles W. Eichelberger