Abstract: A data processing system for processing instructions is shown. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: A method, apparatus, and computer instructions in a processor for selectively performing operations on data. An operation to be performed on data is identified to form an identified operation. A determination is made as to whether metadata identifying a state of the data is associated with the data. A determination is made as to whether the identified operation can be performed on the data based on the state of the data, in response to the metadata being associated with the data. The operation is performed on the data if the state of the data allows for the operation to be performed. The processor selectively performs the operations based on the state of the data.

Abstract: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting of events associated with execution of those instructions or events associated with accesses to those memory locations. The performance information that has been dynamically gathered from the assisting hardware is available to the software application during runtime in order to autonomically affect the behavior of the software application, particularly to enhance its performance. For example, the counted events may be used to autonomically control an execution-path selection within the software application.

Abstract: A method and apparatus for identifying a minimum call tree data structure from a plurality of call tree data structures are provided. With the apparatus and method, call tree data structures are generated for two or more executions of a build of a computer program. The apparatus and method perform a “tree-minimization” operation in which the two or more call trees generated during runs of the computer program are walked and only those nodes that are present in each of the tree data structures are maintained in a minimized tree data structure. In addition, the minimum values for these common nodes are maintained in the minimized tree data structure. In this way, asynchronous events are removed from the minimum tree data structure and analysis may focus on those areas of the computer program that are consistent between runs of the computer program.

Abstract: A method and apparatus for identifying a minimum call tree data structure from a plurality of call tree data structures are provided. With the apparatus and method, call tree data structures are generated for two or more executions of a build of a computer program. The apparatus and method perform a “tree-minimization” operation in which the two or more call trees generated during runs of the computer program are walked and only those nodes that are present in each of the tree data structures are maintained in a minimized tree data structure. In addition, the minimum values for these common nodes are maintained in the minimized tree data structure. In this way, asynchronous events are removed from the minimum tree data structure and analysis may focus on those areas of the computer program that are consistent between runs of the computer program.

Abstract: Illustrative embodiments cover a data processing system for processing instructions and monitoring accesses to memory location ranges. An instruction for execution is identified. A determination is made as to whether the instruction is within a contiguous range of instructions. Execution information relating to the instruction is identified if the instruction is within the contiguous range of instructions. With memory location accesses, an access to a memory location is identified. A determination of whether the memory location is within a contiguous range of memory locations is made. Access information is identified if the memory location is within the contiguous range of memory locations.

Abstract: Hardware assist to autonomically patch code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: A method and apparatus for automatically performing regression processing on trace data are provided. With the apparatus and method, call tree data structures are generated for two or more executions of two or more builds of a computer program. The apparatus and method perform a “tree-minimization” operation on each set of call tree data structures for each of the builds to generate minimized call tree data structures for each build of the computer program. The minimized call tree data structures are then subtracted from one another to generate a subtracted minimized call tree data structure. From this subtracted minimized call tree data structure, the portions of the computer program that are different from build to build and which appreciably and consistently affect the difference in execution of the computer program from build to build may be identified.

Abstract: Hardware assist to autonomically patch code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: A method, apparatus, and computer instructions for providing hardware assistance to prefetch data during execution of code by a process or in the data processing system. In response to loading an instruction in the code into a cache, a determination is made by a processor unit as to whether a prefetch indicator is associated with the instruction. In response to the prefetch indicator being associated with the instruction, a pointer to a data structure identified by the prefetch indicator is selectively prefetched into the cache in the processor.

Abstract: A method, apparatus, and computer instructions for determining computer flows autonomically using hardware assisted thread stack and cataloged symbolic data. When a new thread is spawned during execution of a computer program, new thread work area is allocated by the operating system in memory for storage of call stack information for the new thread. Hardware registers are set with values corresponding to the new thread work area. Upon context switch, values of the registers are saved in a context save area for future restoration. When call stack data is post-processed, the operating system or a device driver copies call stack data from the thread work areas to a consolidated buffer and each thread is mapped to a process. Symbolic data may be obtained based on the process identifier and address of the method/routine that was called/returned in the thread. Corresponding program flow is determined using retrieved symbolic data and call stack data.

Abstract: A method, apparatus, and computer instructions in a processor for selectively performing operations on data. An operation to be performed on data is identified to form an identified operation. A determination is made as to whether metadata identifying a state of the data is associated with the data. A determination is made as to whether the identified operation can be performed on the data based on the state of the data, in response to the metadata being associated with the data. The operation is performed on the data if the state of the data allows for the operation to be performed. The processor selectively performs the operations based on the state of the data.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: A method, apparatus, and computer instructions in a data processing system for monitoring the execution of instructions and accesses to memory locations. If an instruction is associated with a indicator, a counter associated with the instruction is incremented in response to detecting execution of the instruction. The indicator may be associated with a memory location with a counter associated with the memory location being incremented in response to an access of the memory location.

Abstract: A computer implemented method, apparatus, and computer usable program code to collect information for a system or processor having a transition between an idle state and a non-idle state to form collected system or processor information. The collected system or processor information is provided for analysis by an application. Idle counts occurring during execution of code are collected. The idle counts are provided to an application for analyzing why a processor becomes idle.

Abstract: A method, apparatus, and computer instructions for presenting coverage data for code. The coverage data containing instruction access indicators associated with the code is obtained. Particular instruction access indicators that have been set by a processor in the data processing system in response to execution of the code by the processor are identified to form set instruction access indicators. Each set instruction access indicator is associated with a portion of the code. A presentation for the coverage data is generated. The set instruction access indicators are identified in the presentation. This presentation may be, for example, a graphical presentation.

Abstract: A computer implemented method, apparatus, and computer usable code for identifying processor utilization. A current event is detected. A number of elapsed cycles for a processor since a previous event are identified in response to detecting the current event. An elapsed time using the number of elapsed cycles and a current frequency of the processor is calculated, wherein the elapsed time is used to identify the processor utilization.

Abstract: A method, apparatus, and computer instructions in a processor for selectively performing operations on data. An operation to be performed on data is identified to form an identified operation. A determination is made as to whether metadata identifying a state of the data is associated with the data. A determination is made as to whether the identified operation can be performed on the data based on the state of the data, in response to the metadata being associated with the data. The operation is performed on the data if the state of the data allows for the operation to be performed. The processor selectively performs the operations based on the state of the data.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.