Abstract: An FET complementary pair provides the output to a data line. A data input line is coupled to the gate of the P-FET via an OR gate configuration, and to the gate of the N-FET via an AND gate configuration. The output of each gate configuration is cross-connected to an input of the other. When the input data state changes, the two gate configurations provide delays which are effectively in tandem, so that the FET which was ON is first turned OFF, and after a short delay the other is turned ON. This delay ensures that both FET's are not ON at the same time, which prevents an undesirable power flow. To provide a high impedance "float" state, an enable input and its complement are connected to the AND and OR gate configurations respectively.

Abstract: A priority determining network to concurrently arbitrate between a plurality of requests that are initiated by different users who each desire either access to a system (e.g. a computer, a communication system, or the like) or interruption of transfer of data between certain components (e.g. a memory) that are shared by various facilities of the system. Each user is assigned a respective priority number, the magnitude of which determines the order in which the users gain control of the system. Coded signals which correspond to bits of each user's priority number are stored in respective user register means. Each user has an arbitration circuit that comprises a plurality of serially interconnected arbitration stages, which stages are connected between the user's register means and respective ones of a multi-line bus. The bus lines are common to the arbitration circuits of all competing users. Each arbitration stage is connected to receive one bit of a respective user's priority number.

Abstract: An "on chip" substrate bias generator circuit to automatically compensate for threshold variations of devices that form a MOS circuit. The substrate bias generator includes a voltage doubler (or trippler) to develop a wide range of negative bias voltage to be fed back via the substrate to the MOS circuit to provide uniform bias control of the circuit devices.

Abstract: An improved, compact, power saving data latch having utilization as a synchronizer circuit or as a circuit to sample and store input data for subsequent signal processing. The presently improved data latch is fabricated by means including a static flip-flop cell. A transmission gate is connected between an input terminal of the flip-flop cell and a source of input data. A source of clock signals is connected to another input terminal of the flip-flop cell and to a control electrode of the transmission gate to control the conductivity of the transmission gate and the sampling of input data by the flip-flop cell.

Abstract: An improved memory cell for minimizing space consumption and cost of production. A two-rail data bus line configuration is shared for the dual purpose of reading and writing binary information or for powering the memory cell. The memory cell is rendered in a dynamic condition for reading or writing binary information via the data bus lines. At all other times, the memory cell is rendered in a static or holding condition during which time the data nodes of the cell are connected to a source of reference potential and the memory cell is powered.

Abstract: A unique sense circuit to implement a differential memory detector having increased sensitivity for reading the binary state of selected memory cells forming an array thereof. The detector, in a preferred embodiment, includes a circuit comprised of a plurality of metal oxide semiconductor field effect transistors fabricated from a layer of silicon on sapphire (SOS/FETs). The body node of each of a pair of SOS/FETs is respectfully connected to a data bus line of the memory array so as to form differential input nodes to the detector circuit. The instant detector circuit provides relatively large digital output signals from relatively small input signals supplied from the array of memory cells via the data bus lines.