Patents by Inventor Robert K. Montoye

Robert K. Montoye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140026008
    Abstract: A system for programming a phase change material-content addressable memory (PCM-CAM). The system includes a receiving unit for receiving a word to be written in the PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The system includes a writing unit configured to repeatedly write the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and to write high bits in memory cells of the PCM-CAM only once.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li, Robert K. Montoye
  • Publication number: 20140022851
    Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
    Type: Application
    Filed: August 13, 2012
    Publication date: January 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Chung H. Lam, Jing Li, Robert K. Montoye
  • Patent number: 8629705
    Abstract: A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Robert H. Dennard, Brian L. Ji, Wing K. Luk, Robert K. Montoye
  • Publication number: 20130338998
    Abstract: A regular expression matcher system, including: a deterministic finite state machine (DFSM); a ternary content addressable memory (TCAM) matcher to compare a word stored at the TCAM matcher to an input stream, wherein the word determines a state-to-state transition of the DFSM from a comparison result; a programmable logic connected to an output of the TCAM matcher to identify a next state in the DFSM based on the comparison result; a state register to update a current state of the DFSM to the next state; and a collection data structure coupled to the TCAM matcher and the programmable logic to store a sequence of required state transitions for the DFSM, wherein the programmable logic determines a next required state transition to be matched from the sequence.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard F. Freitas, Robert K. Montoye, Rajendra Shinde
  • Publication number: 20130328592
    Abstract: A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: LELAND CHANG, ROBERT K. MONTOYE, YUTAKA NAKAMURA
  • Publication number: 20130328593
    Abstract: A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.
    Type: Application
    Filed: July 9, 2013
    Publication date: December 12, 2013
    Inventors: Leland Chang, Robert K. Montoye, Yutaka Nakamura
  • Patent number: 8604832
    Abstract: A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Robert K. Montoye, Yutaka Nakamura
  • Patent number: 8560902
    Abstract: A method for programming a Phase Change Material-Content Addressable Memory (PCM-CAM). The method includes receiving a word to be written in a PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The method further includes repeatedly writing the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and writing the high bits in memory cells of the PCM-CAM only once.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li, Robert K. Montoye
  • Patent number: 8555119
    Abstract: A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Jente B. Kuang, Robert K. Montoye, Hung C. Ngo, Kevin J. Nowka
  • Publication number: 20130223121
    Abstract: A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: International Business Machines Corporation
    Inventors: Leland Chang, Chung H. Lam, Jing Li, Robert K. Montoye
  • Patent number: 8493093
    Abstract: A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Robert K. Montoye, Yutaka Nakamura
  • Publication number: 20130151818
    Abstract: A method and system for improving performance and latency of instruction execution within an execution pipeline in a processor. The method includes finding, while decoding an instruction, a pointer register used by the instruction; reading the pointer register; validating a pointer register entry; reading, if the pointer register entry is valid, a register file entry; validating a register file entry; validating, if the register file entry is invalid, a valid register file entry wherein the valid register file entry is in the register file's future file; bypassing, if the valid register file entry is valid, a valid register file value from the register file's future file to the execution pipeline wherein the valid register file value is in the valid register file entry; and executing the instruction using the valid register file value; wherein at least one of the steps is carried out using a computer device.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: International Business Machines Corporation
    Inventors: Erez Barak, Alejandro Rico Carro, Jeffrey H. Derby, Amit Golander, Omer Heymann, Nadav Levison, Sagi Manole, Robert K. Montoye
  • Patent number: 8395438
    Abstract: An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Brian L. Ji, Robert K. Montoye
  • Publication number: 20120317062
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 13, 2012
    Applicant: International Business Machines Corporation
    Inventors: Bernard V. BREZZO, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20120301977
    Abstract: A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
    Type: Application
    Filed: August 8, 2012
    Publication date: November 29, 2012
    Applicant: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Harm Peter Hofstee, George A. Katopis, John Ulrich Knickerbocker, Robert K. Montoye, Chirag S. Patel
  • Patent number: 8295056
    Abstract: A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Harm Peter Hofstee, George A. Katopis, John Ulrich Knickerbocker, Robert K. Montoye, Chirag S. Patel
  • Publication number: 20120265967
    Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.
    Type: Application
    Filed: March 21, 2012
    Publication date: October 18, 2012
    Applicant: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Robert K. Montoye, Brett Olsson, John-David Wellman
  • Publication number: 20120262226
    Abstract: An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
    Type: Application
    Filed: June 26, 2012
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Dennard, Brian L. Ji, Robert K. Montoye
  • Publication number: 20120260062
    Abstract: A method and system for providing dynamic addressability of data elements in a vector register file with subword parallelism. The method includes the steps of: determining a plurality of data elements required for an instruction; storing an address for each of the data elements into a pointer register where the addresses are stored as a number of offsets from the vector register file's origin; reading the addresses from the pointer register; extracting the data elements located at the addresses from the vector register file; and placing the data elements in a subword slot of the vector register file so that the data elements are located on a single vector within the vector register file; where at least one of the steps is carried out using a computer device so that data elements in a vector register file with subword parallelism are dynamically addressable.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey H. Derby, Robert K. Montoye
  • Publication number: 20120259804
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 11, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno