Patents by Inventor Robert Kuo-Chang Yang

Robert Kuo-Chang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865727
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 9, 2018
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Publication number: 20170062606
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 2, 2017
    Applicant: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Patent number: 9496386
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 15, 2016
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Publication number: 20150340454
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Application
    Filed: August 3, 2015
    Publication date: November 26, 2015
    Applicant: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Patent number: 9117899
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 25, 2015
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Publication number: 20140145245
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Patent number: 8704296
    Abstract: In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 22, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Robert Kuo-Chang Yang
  • Patent number: 8592906
    Abstract: A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: November 26, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mohamed N. Darwish, Robert Kuo-Chang Yang
  • Patent number: 8580644
    Abstract: A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Publication number: 20130221429
    Abstract: In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Inventor: Robert Kuo-Chang Yang
  • Publication number: 20120211834
    Abstract: A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
    Type: Application
    Filed: May 1, 2012
    Publication date: August 23, 2012
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Publication number: 20120146140
    Abstract: A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 14, 2012
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Mohamed N. Darwish, Robert Kuo-Chang Yang
  • Patent number: 8193565
    Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Publication number: 20120091516
    Abstract: Voltage termination structures include one or more capacitively coupled trenches, which can be similar to the trenches in the drift regions of the active transistor. The capacitively coupled trenches in the termination regions are arranged with an orientation that is either parallel or perpendicular to the trenches in the active device drift region. The Voltage termination structures can also include capacitively segmented trench structures having dielectric lined regions filled with conducting material and completely surrounded by a silicon mesa region. The Voltage termination structures can further include continuous regions composed entirely of an electrically insulating layer extending a finite distance vertically from the device surface.
    Type: Application
    Filed: April 11, 2011
    Publication date: April 19, 2012
    Inventors: Robert Kuo-Chang Yang, Sunglyong Kim, Joseph A. Yedinak
  • Patent number: 8080848
    Abstract: According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: December 20, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mohamed N. Darwish, Robert Kuo-Chang Yang
  • Publication number: 20100123171
    Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
    Type: Application
    Filed: April 17, 2009
    Publication date: May 20, 2010
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Patent number: 7535057
    Abstract: Floating trenches are arranged in the layout of a single DMOS transistor or an array of DMOS transistors, the array forming a single power transistor. The trenches run perpendicular to the gate width direction either outside the transistor(s) or between rows of the transistors. The floating trenches are at a potential between the drain voltage and the substrate voltage (usually ground). The potentials of the opposing trenches cause merging depletion regions in the drift region. This merging shapes the field lines so as to increase the breakdown voltage of the transistor and provide other advantages. The technique is applicable to both lateral and vertical DMOS transistors.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: May 19, 2009
    Inventor: Robert Kuo-Chang Yang
  • Patent number: 7514743
    Abstract: One or more vertical DMOS transistors, such as trench FETS, are formed between opposing floating poly-filled trench portions. The opposing trench portions may include two parallel trenches, rectangular trenches, hexagonal trenches, octagonal trenches, circular trenches, or other shapes. The floating trench portions are capacitively coupled to assume a potential somewhere between the high drain voltage (below the trenches) and the body voltage (near the top of the trenches). The floating trench portions will have a potential below the drift region and deplete the drift region. The depletion regions caused by the opposing trench portions will merge under the gate with a sufficiently high drain voltage. The electric field lines in the drift region will be shaped to increase the breakdown voltage of the device.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 7, 2009
    Inventor: Robert Kuo-Chang Yang
  • Publication number: 20080296636
    Abstract: According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage.
    Type: Application
    Filed: June 2, 2008
    Publication date: December 4, 2008
    Inventors: Mohamed N. Darwish, Richard A. Harris, Muhammed Ayman Shibib, Andrew J. Morrish, Robert Kuo-Chang Yang