Patents by Inventor Robert L. Sankman

Robert L. Sankman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985080
    Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Pramod Malatkar, Kyle Yazzie, Naga Sivakumar Yagnamurthy, Richard J. Harries, Dilan Seneviratne, Praneeth Akkinepally, Xuefei Wan, Yonggang Li, Robert L. Sankman
  • Publication number: 20210043588
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 11, 2021
    Inventors: Lijiang Wang, Jianyong Xie, Sujit Sharan, Robert L. Sankman
  • Publication number: 20210043570
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Publication number: 20210035911
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Publication number: 20210028116
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 28, 2021
    Inventors: Sanka GANESAN, Robert L. SANKMAN, Arghya SAIN, Sri Chaitra Jyotsna CHAVALI, Lijiang WANG, Cemil GEYIK
  • Publication number: 20210028080
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Srinivas PIETAMBARAM, Robert L. Sankman, Rahul Manepalli, Gang Duan, Debendra Mallik
  • Publication number: 20200395300
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Biancun Xie, Jianyong Xie, Sujit Sharan, Debendra Mallik, Robert L. Sankman
  • Publication number: 20200395352
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: June 4, 2020
    Publication date: December 17, 2020
    Inventors: Robert L. Sankman, Sairam Agraharam, Shengquan Ou, Thomas J. De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Publication number: 20200388603
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Inventors: Robert L. Sankman, Pooya Tadayon, Weihua Tang, Chandra M. Jha, Zhimin Wan
  • Publication number: 20200388582
    Abstract: An integrated-circuit package substrate includes a pseudo-stripline that is shielded below a lower solder-resist layer and an upper solder-resist layer, where an upper shielding plane is sandwiched between the lower and upper solder-resist layers. The lower solder-resist layer can at least partially overlap a landing-pad region of a landing-pad via that penetrates a top build-up layer which is contacted by the lower solder-resist layer.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Lilia May, Robert Alan May, Amruthavalli Pallavi Alur, Robert L. Sankman
  • Publication number: 20200335444
    Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard C. Stamey
  • Patent number: 10811366
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Publication number: 20200312767
    Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Srinivas V. Pietambaram, Tarek Ibrahim, Kristof Darmawikarta, Rahul N. Manepalli, Debendra Mallik, Robert L. Sankman
  • Publication number: 20200312833
    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Applicant: INTEL CORPORATION
    Inventors: WILFRED GOMES, MARK T. BOHR, RAJESH KUMAR, ROBERT L. SANKMAN, RAVINDRANATH V. MAHAJAN, WESLEY D. MC CULLOUGH
  • Publication number: 20200303310
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 24, 2020
    Inventors: Amruthavalli Pallavi ALUR, Sri Ranga Sai BOYAPATI, Robert Alan MAY, Islam A. SALAMA, Robert L. SANKMAN
  • Publication number: 20200303822
    Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.
    Type: Application
    Filed: September 29, 2017
    Publication date: September 24, 2020
    Inventors: Jimin YAO, Shawna M. LIFF, William J. LAMBERT, Zhichao ZHANG, Robert L. SANKMAN, Sri Chaitra J. CHAVALI
  • Patent number: 10763215
    Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard C. Stamey
  • Publication number: 20200273721
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Robert L. Sankman, John S. Guzek
  • Publication number: 20200273784
    Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.
    Type: Application
    Filed: December 30, 2017
    Publication date: August 27, 2020
    Inventors: Debendra MALLIK, Robert L. SANKMAN, Robert NICKERSON, Mitul MODI, Sanka GANESAN, Rajasekaran SWAMINATHAN, Omkar KARHADE, Shawna M. LIFF, Amruthavalli ALUR, Sri Chaitra J. CHAVALI
  • Publication number: 20200273783
    Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a base die disposed on an interposer. The semiconductor package also has a plurality of dies on top of one another to form a stack on the base die. Each die has a top surface and a bottom surface that is opposite from the top surface, and each die has one or more die contacts on at least one of the top surface and the bottom surface that are each electrically coupled to at least one die contact of the base die with one or more wire bonds. The semiconductor package includes a mold layer disposed over and around the plurality of dies, the base die, and the one or more wire bonds. The base die may have a first surface area that exceeds a second surface area of the plurality of stacked dies.
    Type: Application
    Filed: December 30, 2017
    Publication date: August 27, 2020
    Inventors: Robert L. SANKMAN, Sanka GANESAN