Patents by Inventor Robert M. Reinschmidt

Robert M. Reinschmidt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7274209
    Abstract: A circuit for shifting a signal from a first voltage level to a second voltage level. In one embodiment, a voltage translator circuit has first and second transistors that are cross-coupled; a third transistor having a gate coupled with the input signal, the third transistor being coupled between the gate of the second cross-coupled transistor and the drain of the first cross-coupled transistor; and a fourth transistor having a gate coupled with an inverted version of the input signal, the fourth transistor being coupled between the gate of the first cross-coupled transistor and the drain of the second cross-coupled transistor. In another embodiment, the circuit may have, as part of its output stage, a first and second output transistors connected in series, and a third output transistor coupled between the second output transistor and ground, the third output transistor having a gate coupled with a high voltage supply.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: September 25, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventor: Robert M. Reinschmidt
  • Patent number: 7196550
    Abstract: A circuit for driving a pair of input signals to form driven output signals while reducing the amount of skew between the driven output signals. In one embodiment, a driver circuit includes a first set of drivers connected in series and receiving the first input signal to produce a first output signal; a second set of drivers connected in series and receiving the second input signal to produce a second output signal; a first transmission gate connecting an input of one of the drivers from the first set of drivers to an output of one of the drivers of the second set of inverters; and a second transmission gate connecting an input of one of the drivers from the second set of drivers to an output of one of the drivers of the first set of drivers. Each transmission gate may be provided with a control for enabling or disabling the transmission gate, thereby permitting the selective application of the de-skew function of the circuit and providing for reduced power consumption when the de-skew function is disabled.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: March 27, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventor: Robert M. Reinschmidt
  • Patent number: 7126398
    Abstract: A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The apparatus may further include a second circuit coupled to the first circuit to drive the first circuit. The second circuit may comprise at least one of a latch and a feedback device.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: October 24, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Eric H. Voelkel, Robert M. Reinschmidt, Greg J. Landry
  • Patent number: 7120884
    Abstract: A mask identification (ID) bit circuit (100) is disclosed that provides one of two potentials (VGND or VPWR) to a sense node (108). A mask ID bit circuit (100) may include a number of links (102-0 to 102-4) arranged in series. A link (102-0 to 102-4) may include inputs (104-0 and 104-1) and outputs (106-0 and 106-1). In one configuration, inputs (104-0 and 104-1) may be directly coupled to outputs (106-0 and 106-1). In another configuration, inputs (104-0 and 104-1) may be cross coupled to outputs (106-0 and 106-1). Cross coupling inputs (104-0 and 104-1) and outputs (106-0 and 106-1) of a link (102-0 to 102-4) can switch a potential (VGND or VPWR) supplied to a sense node (108). The configuration of more than one link (102-0 to 102-4) of a mask ID bit circuit (100) can be changed, allowing a sense node to be switched between two potential (VGND and VPWR) multiple times. According to an embodiment, n mask ID bit circuits (100) may provide as many as 2n different mask ID codes.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: October 10, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Robert M. Reinschmidt, Ronald W. Choi
  • Patent number: 7088166
    Abstract: A low voltage differential signal (LVDS) input circuit with extended common mode range has been disclosed. One embodiment of the LVDS input circuit includes a first resistor coupled between a differential logic circuit and a first input pad, a second resistor coupled between the differential logic circuit and a second input pad, and a first and a second termination resistors coupled to the first and the second input pads, respectively, the first and second termination resistors being coupled to each other in series at a node to produce a common mode reference voltage at the node. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: August 8, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Robert M. Reinschmidt, Dilip Krishnamurthy
  • Patent number: 7068077
    Abstract: A LVDS output driver has been disclosed. One embodiment of the LVDS output driver includes a number of source followers, each of the source followers including a pull-down transistor having a source, a drain, a gate, and a bulk terminal. The embodiment of the LVDS output driver further includes a number of pull-up transistors, each of the pull-up transistors having a source, a drain, and a gate, wherein the drain of each of the pull-up transistors is coupled to the source of a pull-down transistor of the source followers, to output a number of differential signals via the drains of the pull-up transistors. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: June 27, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventor: Robert M. Reinschmidt
  • Patent number: 6486712
    Abstract: A programmable switch includes at least one or more pass transistors having a control voltage that is greater than the data path reference voltage that is selected by a corresponding pass transistor. The control voltage is provided by a higher voltage power supply than the power supply that provides the data path reference voltage. In one embodiment, the higher voltage supply is a quiet supply that is not loaded with devices that switch during normal operation of the programmable switch such as CMOS devices. In another embodiment, the power supply that provides a voltage to an I/O circuit of the probable switch is the power supply that is utilized to provide the control voltage to the pass transistors. In a particular embodiment, the pass transistors comprise higher voltage tolerant devices than other devices in the programmable device. In a particular embodiment, the higher voltage supply is at least the data path reference voltage plus the threshold voltage of the pass transistors.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: November 26, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: Greg J. Landry, Robert M. Reinschmidt, Timothy M. Lacey
  • Publication number: 20020084331
    Abstract: A mask identification (ID) bit circuit (100) is disclosed that provides one of two potentials (VGND or VPWR) to a sense node (108). A mask ID bit circuit (100) may include a number of links (102-0 to 102-4) arranged in series. A link (102-0 to 102-4) may include inputs (104-0 and 104-1) and outputs (106-0 and 106-1). In one configuration, inputs (104-0 and 104-1) may be directly coupled to outputs (106-0 and 106-1). In another configuration, inputs (104-0 and 104-1) may be cross coupled to outputs (106-0 and 106-1). Cross coupling inputs (104-0 and 104-1) and outputs (106-0 and 106-1) of a link (102-0 to 102-4) can switch a potential (VGND or VPWR) supplied to a sense node (108). The configuration of more than one link (102-0 to 102-4) of a mask ID bit circuit (100) can be changed, allowing a sense node to be switched between two potential (VGND and VPWR) multiple times. According to an embodiment, n mask ID bit circuits (100) may provide as many as 2n different mask ID codes.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Robert M. Reinschmidt, Ronald W. Choi
  • Patent number: 5832294
    Abstract: A dual-microprocessor module includes two microprocessors each of a kind which has two selectable modes of operation, an independent mode in which it can operate independently and a cooperative mode in which it can cooperate with another microprocessor when interconnected in a predefined way with the other microprocessor. Conductors interconnect the microprocessors in the predefined way for operation in the cooperative mode. A housing supports the microprocessors and the conductors. An array of pins are used to mount the module in a socket on a circuit board and the pins are connected to the microprocessors. A socket/circuit board combination includes a socket having an array of holes for receiving pins of a microprocessor package.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: November 3, 1998
    Assignee: MicroModule Systems
    Inventor: Robert M. Reinschmidt
  • Patent number: 5301163
    Abstract: A selection circuit for a bipolar ECL memory having memory cell connected to cell selection lines and, more particularly, to upper and lower wordlines. The circuit includes a line driver connected to the upper wordline, an input stage for controlling the line driver to activate the upper wordline connected thereto in response to an address signal, and a switching device responsive to the input stage for applying a discharging current to the lower word line to speed up deactivation of the memory cell in response to a change in the address signal. In one embodiment, the line driver is also turned on at an increased rate for a limited time following application of the address signal to speed up the activation of the line.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: April 5, 1994
    Assignee: Digital Equipment Corp.
    Inventors: Robert M. Reinschmidt, Steven C. Sullivan
  • Patent number: 5289409
    Abstract: Bipolar transistor memory cell and method for use in a random access memory. A pair of state elements are cross coupled so that they assume opposite states in accordance with signals applied thereto, a pair of bipolar pass transistors are connected to respective ones of the state elements for applying signals to the state elements, and current flow through the pass transistors is monitored to determine the states of the state elements.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: February 22, 1994
    Assignee: Digital Equipment Corporation
    Inventor: Robert M. Reinschmidt
  • Patent number: 4864540
    Abstract: A bipolar random access memory having no write recovery time. During a data write operation, while the memory state of the memory cell is being shifted, a data bypass circuit sets a sense latch in the sense amplifier to store the new state to which the memory cell is being set. To prevent the sense latch from being shifted by transient write recovery currents charging bit line parasitic capacitances following the data write operation, a read/write transmission circuit isolates the sense amplifier from the bit lines, diverts current from the sense amplifier to a source of high voltage to charge the parasitic capacitances, and then realigns the sense amplifier to the bit lines.
    Type: Grant
    Filed: February 11, 1988
    Date of Patent: September 5, 1989
    Assignee: Digital Equipment Corporation
    Inventors: A. David Hashemi, Robert M. Reinschmidt
  • Patent number: 4853898
    Abstract: A bipolar RAM having improved read and write cycle times. During a write operation, the state of a selected memory cell is sensed by read/write current controller circuits. A high write current is selected if the data to be written requires a shift of the memory state of the memory cell, and a low write current is selected if the data to be written corresponds to the present memory state of the memory cell. This improves the write cycle time by reducing saturation of the memory cell. If a long write signal is impressed on the RAM, the read/write current controller circuit terminates the high level write current after the memory cell has shifted its memory state. When a memory cell is being selected for a read or write operation, the write current select circuit discharges the bit line attached to the low voltage side of the selected memory cell, improving the read cycle time.
    Type: Grant
    Filed: February 11, 1988
    Date of Patent: August 1, 1989
    Assignee: Digital Equipment Corporation
    Inventors: A. David Hashemi, Robert M. Reinschmidt
  • Patent number: 4663741
    Abstract: An integrated circuit memory system having an array of ECL memory cells, an address circuit, a READ/WRITE circuit and a coupling circuit which increases the operating current of an addressed memory cell during a READ/WRITE operation. The increased operating current is short enough to prevent an excessive saturation of the memory cell transistors. The addressed memory cells remain in a low operating current sufficient to maintain the memory cells in their particular states. Since timing is critical, timing circuits for a system clock are also part of the memory system.
    Type: Grant
    Filed: October 16, 1984
    Date of Patent: May 5, 1987
    Assignee: Trilogy Systems Corporation
    Inventors: Robert M. Reinschmidt, Wylie J. Plummer
  • Patent number: 4617475
    Abstract: A wired voting circuit is described providing an output which follows the majority of input logic levels according to the equation: F=AB+AC+BC. A non-inverting signal voting node (D) and an inverting signal voting node (E) comprise a first and a second collector of an odd number of input differential transistor pairs (30, 32, 34) wherein said nodes are formed by wiring all of said first collectors together at one signal node and by wiring all of said second collectors together at the other signal node. Each signal node is coupled to a differential input of an output differential transistor pair (36). Currents are steered by the state of input logic onto either of the signal nodes, depending upon the input logic signal level. The signal level at each voting node is proportional to the number of input differential transistor pairs that steer current to the voting node. The voting scheme employs an odd number of logic inputs (T, U, V), such that an odd number of currents (I.sub.x, I.sub.y, I.sub.
    Type: Grant
    Filed: March 30, 1984
    Date of Patent: October 14, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventor: Robert M. Reinschmidt
  • Patent number: 4194131
    Abstract: A current mirror transistor is included in a tristate logic buffer circuit, with its base and emitter respectively connected to the base and emitter of the phase splitter transistor and its collector connected to the voltage supply terminal. The emitter size of the current mirror transistor is a multiple of the emitter size of the phase splitter transistor. A high resistance connected between the voltage supply terminal and the collector of the phase splitter transistor provides lower power consumption when the circuit is disabled; and the current mirror transistor supplements the drive current provided by the phase splitter transistor when the circuit is not disabled.
    Type: Grant
    Filed: May 30, 1978
    Date of Patent: March 18, 1980
    Assignee: National Semiconductor Corporation
    Inventors: Dale A. Mrazek, Robert M. Reinschmidt
  • Patent number: 4078261
    Abstract: A bipolar sense-write circuit is provided for sensing voltage levels representative of a logical "1" or a logical "0" stored in a flip-flop storage cell and for writing voltage levels into the flip-flop storage cell. The sense portion of the sense-write circuit is essentially independent of the write portion thereof. The sense circuitry portion of the sense-write circuit includes circuitry for biasing a pair of bit lines at substantially equal voltages at all times, except during a write cycle, to a voltage which facilitates sensing of a selected storage cell and which also results in the write circuitry being essentially electrically isolated from the sense-bit lines during a read cycle. During a write cycle, the read circuitry is effectively disabled so that the bit lines are at voltages determined by the write circuitry, and the read circuitry is effectively isolated from the sense-bit lines during the write cycle, and the write circuitry applies an increased voltage to one of the sense-bit conductors.
    Type: Grant
    Filed: January 2, 1976
    Date of Patent: March 7, 1978
    Assignee: Motorola, Inc.
    Inventors: Michael S. Millhollan, Robert M. Reinschmidt