Abstract: Apparatus for generating and displaying data on a monitor 28 such as a CRT of LCD display. The display is comprised of a plurality of images, each located at positions on the face of the monitor defined by multi-digit coordinate values in a multi-coordinate system. Units of data are stored in linear display memory 26, each such unit of data corresponding to and defining the image to be displayed at one of said positions. The apparatus includes a circuit 60 which places selected bits of said multi-digit coordinate values in a preselected order to define the address or offset in said linear display memory at which is located the corresponding unit of data.

Abstract: A system and method for time slicing multiple received data streams utilizing multiple processors in such a manner as to ensure that all processors are running at full capability and are efficiently timesharing a global memory storage area. The received data streams are each divided into fixed portions called spans. The invention is operable for sequencing the movement of the time-sliced spans between the processors, adjusting the scheduling of particular ones of the time-sliced spans as a function of either processor availability or maintenance of real-time transmission of the received real-time time-sliced data streams.

Abstract: A memory system 107,300 is provided which includes a memory 107 having a data area for storing data words and a mask area 302 for storing a control mask. Mask generation circuitry 301 is provided for generating such a control mask for storage in the mask area 302 of the memory 107. Mask controlled memory read control circuitry 303 is provided which is operable to selectively retrieve from the mask area 302 bits of the mask stored therein and in response selectively retrieve and output data words stored in the data area of the memory 107.

Abstract: Disclosed is a system and method for mixing a plurality of graphics and video signals to create a desired output format, the desired output format being a mixture of the received signals. The mechanisim for achieving this rich format is a multi-modal graphics video overlay controller. The controller having a set of opcodes, selects a subset of the opcode set, this selection being a function of a desired output format of the mixed signals. The subset of opcodes is then utilized to control the means for selectively switching among the received graphics and video signals to create the desired output format. The selective switching is accomplished on a pixel by pixel basis.

Abstract: A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: A memory bandwidth allocation scheme in a computer system having a unified memory architecture. When a first device requesting access to a resource detects that two higher priority devices are also requesting access to the same resource, the first device shuts itself down. Accordingly, the first device deactivates its access request signals and clears its buffers. Then, the first device reactivates itself when it receives a graphics VSYNC signal. This allocation scheme ensures that the arbiter will not get stuck in a loop serving only high priority requests and not serving lower priority requests.

Abstract: An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the BitBLT engine cannot interrupt the transfer of data to the graphics device. Each device capable of issuing memory access requests is categorized into one of four classes. The LWM requests are the highest priority requests, followed by CPU memory access requests, then BitBLT engine requests, and finally by HWM requests. When a LWM request is granted, the requesting device's HWM request is elevated to a priority between the CPU and the BitBLT engine. Once the LWM request is complete, the HWM request is served until either it completes, the CPU issues a memory access request, or another LWM request occurs.