Patents by Inventor Roberto Canegallo

Roberto Canegallo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11342885
    Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 24, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alessia Maria Elgani, Francesco Renzini, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, Giulio Ricotti
  • Publication number: 20220068380
    Abstract: An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 3, 2022
    Inventors: Marcella Carissimi, Marco Pasotti, Roberto Canegallo
  • Patent number: 11119160
    Abstract: A planar Hall sensing element includes a first pair of sensing electrodes mutually opposed in a first direction across the sensing element and a second pair of sensing electrodes mutually opposed in a second direction across the sensing element, with the second direction orthogonal to the first direction. A first pair of bias electrodes is mutually opposed in a third direction and a second pair mutually opposed in a fourth direction across the sensing element, the fourth direction orthogonal to the third direction. The third and fourth directions are rotated 45° with respect to the first and second directions so each sensing electrode is arranged between a bias electrode of the first pair and second pair. A DC bias current is supplied between the first and second pairs of bias electrodes. First and second Hall voltages are sensed at the first and second pairs of sensing electrodes.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: September 14, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Crescentini, Michele Biondi, Marco Tartagni, Aldo Romani, Roberto Canegallo
  • Publication number: 20200177133
    Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Inventors: Alessia Maria Elgani, Francesco Renzini, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, Giulio Ricotti
  • Patent number: 10571531
    Abstract: A Hall sensor may include a Hall sensing element configured to produce a Hall voltage indicative of a magnetic field when traversed by an electric current, and a first pair of bias electrodes mutually opposed in a first direction across the Hall sensing element. The Hall sensor may include a second pair of bias electrodes mutually opposed in a second direction across the Hall sensing element. The Hall sensor may include a first pair of sensing electrodes mutually opposed in a third direction across the Hall sensing element, and a second pair of sensing electrodes mutually opposed in a fourth direction across the Hall sensing element. The fourth direction may be orthogonal to the third direction, each sensing electrode being between a bias electrode of the first pair and a bias electrode of the second pair.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: February 25, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Crescentini, Marco Tartagni, Aldo Romani, Roberto Canegallo, Marco Marchesi, Domenico Cristaudo
  • Publication number: 20200025843
    Abstract: A planar Hall sensing element includes a first pair of sensing electrodes mutually opposed in a first direction across the sensing element and a second pair of sensing electrodes mutually opposed in a second direction across the sensing element, with the second direction orthogonal to the first direction. A first pair of bias electrodes is mutually opposed in a third direction and a second pair mutually opposed in a fourth direction across the sensing element, the fourth direction orthogonal to the third direction. The third and fourth directions are rotated 45° with respect to the first and second directions so each sensing electrode is arranged between a bias electrode of the first pair and second pair. A DC bias current is supplied between the first and second pairs of bias electrodes. First and second Hall voltages are sensed at the first and second pairs of sensing electrodes.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 23, 2020
    Inventors: Marco Crescentini, Michele Biondi, Marco Tartagni, Aldo Romani, Roberto Canegallo
  • Publication number: 20180203076
    Abstract: A Hall sensor may include a Hall sensing element configured to produce a Hall voltage indicative of a magnetic field when traversed by an electric current, and a first pair of bias electrodes mutually opposed in a first direction across the Hall sensing element. The Hall sensor may include a second pair of bias electrodes mutually opposed in a second direction across the Hall sensing element. The Hall sensor may include a first pair of sensing electrodes mutually opposed in a third direction across the Hall sensing element, and a second pair of sensing electrodes mutually opposed in a fourth direction across the Hall sensing element. The fourth direction may be orthogonal to the third direction, each sensing electrode being between a bias electrode of the first pair and a bias electrode of the second pair.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Marco Crescentini, Marco Tartagni, Aldo Romani, Roberto Canegallo, Marco Marchesi, Domenico Cristaudo
  • Patent number: 9952291
    Abstract: A Hall sensor may include a Hall sensing element configured to produce a Hall voltage indicative of a magnetic field when traversed by an electric current, and a first pair of bias electrodes mutually opposed in a first direction across the Hall sensing element. The Hall sensor may include a second pair of bias electrodes mutually opposed in a second direction across the Hall sensing element. The Hall sensor may include a first pair of sensing electrodes mutually opposed in a third direction across the Hall sensing element, and a second pair of sensing electrodes mutually opposed in a fourth direction across the Hall sensing element. The fourth direction may be orthogonal to the third direction, each sensing electrode being between a bias electrode of the first pair and a bias electrode of the second pair.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 24, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Crescentini, Marco Tartagni, Aldo Romani, Roberto Canegallo, Marco Marchesi, Domenico Cristaudo
  • Publication number: 20170030983
    Abstract: A Hall sensor may include a Hall sensing element configured to produce a Hall voltage indicative of a magnetic field when traversed by an electric current, and a first pair of bias electrodes mutually opposed in a first direction across the Hall sensing element. The Hall sensor may include a second pair of bias electrodes mutually opposed in a second direction across the Hall sensing element. The Hall sensor may include a first pair of sensing electrodes mutually opposed in a third direction across the Hall sensing element, and a second pair of sensing electrodes mutually opposed in a fourth direction across the Hall sensing element. The fourth direction may be orthogonal to the third direction, each sensing electrode being between a bias electrode of the first pair and a bias electrode of the second pair.
    Type: Application
    Filed: April 29, 2016
    Publication date: February 2, 2017
    Inventors: Marco CRESCENTINI, Marco TARTAGNI, Aldo ROMANI, Roberto CANEGALLO, Marco MARCHESI, Domenico CRISTAUDO
  • Patent number: 9432020
    Abstract: A communication cell for an integrated circuit includes a physical interface configured to supply an input signal (for example, a capacitive signal or an ohmic signal). A receiver circuit operates to receive the capacitive signal and generate a first intermediate signal. A buffer circuit operates to receive the ohmic signal and generate a second intermediate signal. An output stage including a selector device (for example, a multiplexer) configured to receive the first and second intermediate signals and selectively pass only one of those signals to the integrated circuit based on operating condition. The input signal may further be an inductive signal, with the output stage further functioning to selectively pass that signal based on operating condition.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: August 30, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Roberto Canegallo, Luca Perilli, Luca Perugini, Salvatore Valerio Cani, Eleonora Franchi
  • Publication number: 20150381177
    Abstract: A communication cell for an integrated circuit includes a physical interface configured to supply an input signal (for example, a capacitive signal or an ohmic signal). A receiver circuit operates to receive the capacitive signal and generate a first intermediate signal. A buffer circuit operates to receive the ohmic signal and generate a second intermediate signal. An output stage including a selector device (for example, a multiplexer) configured to receive the first and second intermediate signals and selectively pass only one of those signals to the integrated circuit based on operating condition. The input signal may further be an inductive signal, with the output stage further functioning to selectively pass that signal based on operating condition.
    Type: Application
    Filed: June 19, 2015
    Publication date: December 31, 2015
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Roberto Canegallo, Luca Perilli, Luca Perugini, Salvatore Valerio Cani, Eleonora Franchi
  • Patent number: 9219481
    Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: December 22, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mauro Scandiuzzo, Salvatore Valerio Cani, Claudio Mucci, Roberto Canegallo, Pier Luigi Rolandi
  • Patent number: 9176185
    Abstract: A testing apparatus includes a tester and a probe card system that includes a probe card connected to the tester, and an active interposer connected to the probe card and wirelessly coupled with a device to be tested. The active interposer includes pads positioned on its free surface facing the device. The pads are positioned with respect to pads of the device so that each pad of the active interposer faces a pad of the device and is separated therefrom by a dielectric. Each pair of facing pads forms an elementary wireless coupling element which allows a wireless transmission between the active interposer and the device. The active interposer also includes an amplifier circuit configured to amplify wireless signals from the device before forwarding them to the tester. The probe card system includes a transmission element able to transmit a power voltage from the tester to the device.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: November 3, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Canegallo, Mauro Scandiuzzo, Roberto Cardu, Eleonora Franchi Scarselli, Alberto Pagani
  • Patent number: 9147636
    Abstract: A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: September 29, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Canegallo, Mauro Scandiuzzo, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Guerrieri
  • Publication number: 20150155874
    Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.
    Type: Application
    Filed: February 6, 2015
    Publication date: June 4, 2015
    Inventors: Mauro SCANDIUZZO, Salvatore Valerio CANI, Claudio Mucci, Roberto Canegallo, Pier Luigi Rolandi
  • Patent number: 9001521
    Abstract: An assembly including: a first substrate having a first surface and housing a first electrical-interconnection element and a second electrical-interconnection element in a position corresponding to the first surface; a second substrate having a second surface, housing a third electrical-interconnection element and a fourth electrical-interconnection element in a position corresponding to the second surface, and provided with a dielectric layer extending on top of the third interconnection element; and a first bump and a second bump made of conductive material, extending between the first electrical-interconnection element and the third electrical-interconnection element and, respectively, between the second electrical-interconnection element and the fourth electrical-interconnection element, at least partially aligned to the respective electrical-interconnection elements, the first bump being ohmically coupled to the first interconnection element and capacitively coupled to the third interconnection element,
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Canegallo, Mauro Scandiuzzo
  • Patent number: 8982574
    Abstract: Contactless differential coupling structures can be used to communicate signals between circuits located on separate chips or from one chip to a probing device. The contactless coupling structures avoid problems (breaks, erosion, corrosion) that can degrade the performance of ohmic-type contact pads. The contactless coupling structures comprise pairs of conductive pads placed in close proximity. Differential signals are applied across a first pair of differential pads, and the signals are coupled wirelessly to a mating pair of conductive pads. Circuitry for generating and receiving differential signals is described.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics S.R.L.
    Inventors: Mauro Scandiuzzo, Luca Perilli, Roberto Canegallo
  • Patent number: 8981830
    Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mauro Scandiuzzo, Salvatore Valerio Cani, Claudio Mucci, Roberto Canegallo, Pier Luigi Rolandi
  • Patent number: 8773162
    Abstract: An embodiment of communication cell for enabling data communication between an integrated circuit and an electronic unit distinct from the integrated circuit, comprising a contact pad unit, configured for capacitively coupling, in a first operating condition of said communication cell, to the electronic unit for receiving an input signal from said electronic unit, and for ohmically coupling, in a second operating condition of said communication cell, to the electronic unit for receiving the input signal; a receiver device, including signal-amplifying means, coupled between said contact pad unit and said integrated circuit, configured for receiving the input signal and generating an intermediate signal correlated to the input signal; signal-selection means receiving the intermediate signal, the input signal, and providing an output signal which is the intermediate signal during the first operating condition, and the input signal during the second operating condition; and an input stage, connectable between the
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: July 8, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Canegallo, Roberto Cardu, Mauro Scandiuzzo, Salvatore Valerio Cani, Luca Perugini
  • Patent number: 8411492
    Abstract: A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics S.R.L.
    Inventors: Valentina Nardone, Stefano Pucillo, Roberto Canegallo, Claudio Mucci, Massimiliano Innocenti, Luca Perugini