Patents by Inventor Robertus Laurentius van der Valk
Robertus Laurentius van der Valk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7738501Abstract: A method is disclosed for recovering timing information between master and slave nodes interconnected over a packet network having an underlying time grid with a distinct granularity. A series timing packets are exchanged between said master and slave nodes to measure the time offset of the time grid relative to clocks at the master and slave clocks. This offset is then used to either adjust the local clock at the slave node, or generate the clock using a digital controlled oscillator.Type: GrantFiled: April 10, 2006Date of Patent: June 15, 2010Assignee: Zarlink Semiconductor, Inc.Inventors: Willem L. Repko, Robertus Laurentius Van der Valk
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Patent number: 7728634Abstract: A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB=fCLK2/fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.Type: GrantFiled: July 25, 2008Date of Patent: June 1, 2010Assignee: Zarlink Semiconductor Inc.Inventors: Johannes Hermanus Aloysius De Rijk, Robertus Laurentius van der Valk
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Patent number: 7642862Abstract: A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.Type: GrantFiled: November 14, 2007Date of Patent: January 5, 2010Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius van der Valk, Paul Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
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Patent number: 7619483Abstract: A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.Type: GrantFiled: November 14, 2007Date of Patent: November 17, 2009Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Douglas Robert Sitch
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Publication number: 20090184736Abstract: A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB=fCLK2/fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.Type: ApplicationFiled: July 25, 2008Publication date: July 23, 2009Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Johannes Hermanus Aloysius De Rijk, Robertus Laurentius van der Valk
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Patent number: 7557624Abstract: A phase locked loop provides an output frequency that bears a fractional relationship to an input frequency and includes a controlled oscillator for generating the output frequency. The phase information is scaled in the amplitude domain to provide the fractional relationship.Type: GrantFiled: November 15, 2007Date of Patent: July 7, 2009Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
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Publication number: 20080122504Abstract: A phase locked loop provides an output frequency that bears a fractional relationship to an input frequency and includes a controlled oscillator for generating the output frequency. The phase information is scaled in the amplitude domain to provide the fractional relationship.Type: ApplicationFiled: November 15, 2007Publication date: May 29, 2008Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
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Publication number: 20080116982Abstract: A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.Type: ApplicationFiled: November 14, 2007Publication date: May 22, 2008Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
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Publication number: 20080116980Abstract: A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.Type: ApplicationFiled: November 14, 2007Publication date: May 22, 2008Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Douglas Robert Sitch
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Patent number: 7376156Abstract: Disclosed is a method of aligning clocks over multiple networks having different clock domains. The method comprises transmitting timestamped packets over said networks between source and destination nodes, said timestamped packets conveying timing information based on a source clock at said source node, determining the expected delay over multiple nodes for a given traffic density, identifying at least one intermediate node between said source and destination node where said determined expected delay is such as to permit clock restoration within predefined acceptable parameters, restoring said source clock at said at least one intermediate restoration node to generate a restored intermediate clock signal, producing from said restored intermediate clock signal new timestamped packets conveying timing information based on said restored intermediate clock signal, and forwarding said new timestamped packets to said destination node.Type: GrantFiled: February 18, 2004Date of Patent: May 20, 2008Assignee: Zarlink Semiconductor Inc.Inventors: Willem L. Repko, Robertus Laurentius Van Der Valk, Petrus W. Simons
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Patent number: 7369002Abstract: The present invention is a method to rapidly lock a type II phase locked loop (PLL) after a frequency jump without degrading the output signal much. The method to decrease the settling time and improve the quality of the output clock during the settling disclosed herein comprises of the following broad steps: Estimate new frequency offset with a separate circuit outside the PLL loop to measure the frequency of the input signal accurately. Ramp integrator to the new frequency offset. Do phase build out or phase pull-in. The remaining phase offset is build out when no edge to edge alignment is required. Otherwise, the remaining phase offset is pulled in while the integrator in the PLL's loop filter is disabled. Reduce the PLL bandwidth and/or lower damping to let the PLL settle. Switch the PLL to final bandwidth and damping required by the application.Type: GrantFiled: July 27, 2006Date of Patent: May 6, 2008Assignee: Zarlink Semiconductor, Inc.Inventors: Menno Tjeerd Spijker, Jason Robert Rosinski, Jr., Robertus Laurentius Van Der Valk
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Patent number: 7356036Abstract: Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.Type: GrantFiled: February 18, 2004Date of Patent: April 8, 2008Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius Van Der Valk, Willem L. Repko
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Patent number: 7096243Abstract: A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.Type: GrantFiled: January 21, 2003Date of Patent: August 22, 2006Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk
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Patent number: 7078946Abstract: A resampler filter for use in an analog phase-locked loop has a charge pump and one or more switched capacitors switched by signals derived from a voltage controlled oscillator in the phase locked loop.Type: GrantFiled: December 27, 2002Date of Patent: July 18, 2006Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius van der Valk, Gerrit Dijkstra, Philip Ching
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Publication number: 20040264478Abstract: Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.Type: ApplicationFiled: February 18, 2004Publication date: December 30, 2004Applicant: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius Van Der Valk, Willem L. Repko
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Publication number: 20040223518Abstract: Disclosed is a method of aligning clocks over multiple networks having different clock domains. The method comprises transmitting timestamped packets over said networks between source and destination nodes, said timestamped packets conveying timing information based on a source clock at said source node, determining the expected delay over multiple nodes for a given traffic density, identifying at least one intermediate node between said source and destination node where said determined expected delay is such as to permit clock restoration within predefined acceptable parameters, restoring said source clock at said at least one intermediate restoration node to generate a restored intermediate clock signal, producing from said restored intermediate clock signal new timestamped packets conveying timing information based on said restored intermediate clock signal, and forwarding said new timestamped packets to said destination node.Type: ApplicationFiled: February 18, 2004Publication date: November 11, 2004Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Willem L. Repko, Robertus Laurentius Van Der Valk, Petrus W. Simons
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Patent number: 6795520Abstract: A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.Type: GrantFiled: January 31, 2003Date of Patent: September 21, 2004Assignee: Zarlink Semiconductor Inc.Inventor: Robertus Laurentius Van Der Valk
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Patent number: 6784706Abstract: The method is capable of rapidly bringing a phase-locked loop subject to overshoot into lock after a phase or frequency jump. The phase-locked loop has a phase detector, a controlled oscillator, and an integrator having an output frequency setting that, with the output of said phase detector, determines a frequency setting of the controlled oscillator. The method includes the steps of storing a value for the output frequency setting of the integrator prior to the phase or frequency jump, determining when a phase hit occurs after the phase or frequency jump, and restoring the output frequency setting of the integrator to the stored value on or soon after the phase hit to reduce overshoot. In this way the degradation of PLL performance is minimized.Type: GrantFiled: December 20, 2002Date of Patent: August 31, 2004Assignee: Zarlink Semiconductor, Inc.Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius de Rijk
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Publication number: 20040153894Abstract: A circuit for measuring the accuracy of a clock signal comprising has a first digital phase locked loop receiving an input signal and providing an output signal and a second digital phase locked loop receiving at its input the output signal from the first phase locked loop. One or more measurement terminals are internally connected to one of the phase locked loops to provide a measurement signal.Type: ApplicationFiled: January 21, 2003Publication date: August 5, 2004Applicant: Zarlink Semiconductor Inc.Inventor: Robertus Laurentius van der Valk
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Publication number: 20030177156Abstract: A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.Type: ApplicationFiled: January 21, 2003Publication date: September 18, 2003Applicant: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk