Abstract: A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.

Abstract: Predictive multi-stage modelling for complex semiconductor device manufacturing process control is provided. In one aspect, a method of predictive multi-stage modelling for controlling a complex semiconductor device manufacturing process includes: collecting geometrical data from metrology measurements made at select stages of the manufacturing process; and making an outcome probability prediction at each of the select stages using a multiplicative kernel Gaussian process, wherein the outcome probability prediction is a function of a current stage and all prior stages. Machine-learning models can be trained for each of the select stages of the manufacturing process using the multiplicative kernel Gaussian process. The machine-learning models can be used to provide probabilistic predictions for a final outcome in real-time for production wafers. The probabilistic predictions can then be used to select production wafers for rework, sort, scrap or disposition.

Abstract: An approach for utilizing an IC (integrated circuit) that is capable of storing multi-bit in storage is disclosed. The approach leverages the use of multiple nanowires structures as channels in a gate of a transistor. The use of multiple nanowires as channels allows for different Vt (i.e., voltage of device) to be dependent on the thickness of the fe (ferroelectric layer) that surrounds each of the nanowire channels. Memory window is about 2d (thickness of a fe layer). Setting voltage is also proportional to the fe layer thickness. The Vt of the device is the superposition of the various fe layers. For example, if there are three channels with three different Fe layer (of varying thickness), then four memory states can be achieved. More states can be achieved based on the number of channels in the device.

Abstract: A method for machine learning enhanced optical-based screening for in-line wafer testing includes receiving optical spectra data for a wafer-under-test by performing scatterometry on the wafer-under-test, performing predictive model screening by applying a predictive model based on the optical spectra data, determining whether a device associated with the wafer-under-test is defective based on the predictive model screening, and if the device is determined to be defective, dynamically modifying a yield map associated with the wafer-under-test, including reassigning at least one die.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Techniques for secure and tamper-resistant wafer identification using a unique wafer fingerprint are provided. In one aspect, a method for wafer authentication includes: placing, at each level of fabrication of chips on the wafer, reference structures across the chips; inspecting the wafer at each level of the fabrication; and performing at least one of overlay and scatterometry measurements of the reference structures to use as a unique fingerprint for authenticating the wafer that has been inspected. A method for authentication throughout a process flow for fabrication of chips on a wafer is also provided, as is a wafer having chips and reference structures placed across the chips at each level of the chips to provide a unique fingerprint for authenticating the wafer.

Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

Abstract: Embodiments of the present invention provide an improved method and system for assessing non-uniformity of features in the measurement area (within the beam spot) on a semiconductor structure, (e.g. wafer), such as a non-uniform film thickness. The scattering from non-uniform features is modeled. Post-processing the residual of theoretical and collected spectra is performed to assess a measure of non-uniformity from within an incident spot beam of a spectrum acquisition tool.

Abstract: Predictive multi-stage modelling for complex semiconductor device manufacturing process control is provided. In one aspect, a method of predictive multi-stage modelling for controlling a complex semiconductor device manufacturing process includes: collecting geometrical data from metrology measurements made at select stages of the manufacturing process; and making an outcome probability prediction at each of the select stages using a multiplicative kernel Gaussian process, wherein the outcome probability prediction is a function of a current stage and all prior stages. Machine-learning models can be trained for each of the select stages of the manufacturing process using the multiplicative kernel Gaussian process. The machine-learning models can be used to provide probabilistic predictions for a final outcome in real-time for production wafers. The probabilistic predictions can then be used to select production wafers for rework, sort, scrap or disposition.

Abstract: A technique relates to a semiconductor device. A bottom sacrificial layer is formed on a substrate. A stack is formed over the bottom sacrificial layer and a dummy gate is formed over the stack. The bottom sacrificial layer is removed from under the stack so as to leave an opening. An isolation layer is formed in the opening, the isolation layer being positioned between the stack and the substrate.

Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.

Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.

Abstract: A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.

Abstract: Techniques for measuring defectivity using model-less scatterometry with cognitive machine learning are provided. In one aspect, a method for defectivity detection includes: capturing SEM images of defects from a plurality of training wafers; classifying type and density of the defects from the SEM images; making training scatterometry scans of a same location on the training wafers as the SEM images; training a machine learning model to correlate the training scatterometry scans with the type and density of the defects from the same location in the SEM images; making scatterometry scans of production wafers; and detecting defectivity in the production wafers by measuring the type and density of the defects in the production wafers using the machine learning model, as trained, and the scatterometry scans of the production wafers. A system for defectivity detection is also provided.

Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.