Patents by Inventor Robin Hsin-Kuo Chao

Robin Hsin-Kuo Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10756177
    Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet
  • Patent number: 10756178
    Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet
  • Patent number: 10741639
    Abstract: A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Loubet, Robin Hsin Kuo Chao, Julien Frougier, Ruilong Xie
  • Patent number: 10692203
    Abstract: Techniques for measuring defectivity using model-less scatterometry with cognitive machine learning are provided. In one aspect, a method for defectivity detection includes: capturing SEM images of defects from a plurality of training wafers; classifying type and density of the defects from the SEM images; making training scatterometry scans of a same location on the training wafers as the SEM images; training a machine learning model to correlate the training scatterometry scans with the type and density of the defects from the same location in the SEM images; making scatterometry scans of production wafers; and detecting defectivity in the production wafers by measuring the type and density of the defects in the production wafers using the machine learning model, as trained, and the scatterometry scans of the production wafers. A system for defectivity detection is also provided.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dexin Kong, Robin Hsin Kuo Chao, Huai Huang
  • Patent number: 10658459
    Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, Ruilong Xie, John H. Zhang
  • Publication number: 20200152631
    Abstract: A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.
    Type: Application
    Filed: December 31, 2019
    Publication date: May 14, 2020
    Inventors: Robin Hsin Kuo Chao, Hemanth Jagannathan, Choonghyun Lee, Chun Wing Yeung, II, Jingyun Zhang
  • Patent number: 10636694
    Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie
  • Publication number: 20200105868
    Abstract: A technique relates to a semiconductor device. A bottom sacrificial layer is formed on a substrate. A stack is formed over the bottom sacrificial layer and a dummy gate is formed over the stack. The bottom sacrificial layer is removed from under the stack so as to leave an opening. An isolation layer is formed in the opening, the isolation layer being positioned between the stack and the substrate.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Nicolas LOUBET, Robin Hsin Kuo CHAO, Julien FROUGIER, Ruilong XIE
  • Publication number: 20200105869
    Abstract: A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Nicolas LOUBET, Robin Hsin Kuo CHAO, Julien FROUGIER, Ruilong XIE
  • Publication number: 20200064275
    Abstract: A method for machine learning enhanced optical-based screening for in-line wafer testing includes receiving optical spectra data for a wafer-under-test by performing scatterometry on the wafer-under-test, performing predictive model screening by applying a predictive model based on the optical spectra data, determining whether a device associated with the wafer-under-test is defective based on the predictive model screening, and if the device is determined to be defective, dynamically modifying a yield map associated with the wafer-under-test, including reassigning at least one die.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 27, 2020
    Inventors: Robin Hsin Kuo Chao, Mary Breton, Huai Huang, Dexin Kong, Lawrence A. Clevenger
  • Publication number: 20200044055
    Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Inventors: Chi-Chun Liu, Chun Wing Yeung, Robin Hsin Kuo Chao, Zhenxing Bi, Kristin Schmidt, Yann Mignot
  • Publication number: 20200027984
    Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 23, 2020
    Inventors: Chun Wing Yeung, ChoongHyun Lee, Jingyun Zhang, Robin Hsin Kuo Chao, Heng Wu
  • Patent number: 10529850
    Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chun Wing Yeung, ChoongHyun Lee, Jingyun Zhang, Robin Hsin Kuo Chao, Heng Wu
  • Publication number: 20200006476
    Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.
    Type: Application
    Filed: August 20, 2019
    Publication date: January 2, 2020
    Applicant: International Business Machines Corporation
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, Ruilong Xie, John H. Zhang
  • Publication number: 20190393076
    Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
    Type: Application
    Filed: September 5, 2019
    Publication date: December 26, 2019
    Applicant: International Business Machines Corporation
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie
  • Patent number: 10475905
    Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Chun Wing Yeung, Robin Hsin Kuo Chao, Zhenxing Bi, Kristin Schmidt, Yann Mignot
  • Publication number: 20190326435
    Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.
    Type: Application
    Filed: April 18, 2018
    Publication date: October 24, 2019
    Inventors: Chun Wing Yeung, ChoongHyun Lee, Jingyun Zhang, Robin Hsin Kuo Chao, Heng Wu
  • Patent number: 10453736
    Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie
  • Patent number: 10431651
    Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, Ruilong Xie, John H. Zhang
  • Publication number: 20190280102
    Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 12, 2019
    Inventors: Jingyun Zhang, Choonghyun Lee, Chun Wing Yeung, Robin Hsin Kuo Chao, Heng Wu