Abstract: A stable sine wave oscillator circuit comprising two pairs of cross-coupled bipolar transistors in cascode, the collector electrodes of the transistors of each pair being interconnected by way of respective capacitors. Output signals in phase quadrature may be obtained from across these two capacitors.

Abstract: In a direct conversion receiver in which received radio frequency signals are mixed with quadrature local oscillator signals in I and Q channels, the output signals from the mixers are applied to a phase detector by way of respective frequency tracking filters to reduce the noise bandwidth and improve the sensitivity.

Abstract: A family of wideband amplifier circuits using series and shunt feedback over two stages to achieve constant impedance, including single-ended, single-ended input/differential output and differential input/differential output forms.

Abstract: A fractional-N synthesizer including a phase locked loop comprising: a voltage controlled oscillator (4) providing a loop output signal, the output signal being coupled via an N variable divider (6) to a first input of a phase or frequency detector (8); a reference frequency source coupled to a second input of the phase or frequency detector (8), the detector providing at an output a control signal, in dependence upon a comparision between the signals applied to the first and second inputs, for application to a control input of the voltage controlled oscillator (4); and means for setting the division ratio (N) of the variable divider (6) in response to a frequency data word, including interpolator means (50) for periodically varying at least the LSB of the frequency data word, the interpolator means (50) comprising an input for receiving said LSB, a combiner means (70, 80) for comparing the LSB with a feedback signal, and a quantizer circuit (72, 84) and a filter circuit (74, 82) providing a predetermined del

Abstract: An oscillator of balanced design in which a resonant impedance network is connected between the control ports of two matched transistors, and a capacitance is connected in parallel, across the two inputs of these transistors. The inputs of the transistors are connected each to a matched current source. The signals at the transistor outputs are summed together at a common node. Signals of resonant frequency in each arm of the oscillator are equal in magnitude but opposite in phase. Signals at resonant frequency thus cancel whereas signals at the second harmonic frequency add constructively and are thus enhanced. The effect is a net frequency doubling. For high frequency operation, bipolar transistors are utilized. The current sources can be modulated and an IF mixer output derived. Signal of resonant frequency can be extracted and used for signal prescaling. In an equivalent arrangement, an inductance and resonant network replace the resonant network and capacitance just mentioned.

Abstract: A capacitor simulator circuit comprises a first node, a first capacitor coupled between a second node and a reference potential, a second capacitor coupled between a third node and a reference potential, a resistor coupled between the first and third nodes, a first electrical switch arranged when in an open state to electrically isolate from one another the first and second nodes and when in a closed state to electrically coupled together the first and second nodes, a second electrical switch arranged when in an open state to electrically isolate from one another the second and third nodes and when in a closed state to electrically couple together the second and third nodes.

Abstract: An arrangement for suppressing amplitude variation in FM signals comprises a frequency divider which frequency divides an incoming FM signal to provide frequency divided signals having two discrete levels dependent upon the amplitude of the incoming FM signal in relation to a threshold value, and a frequency multiplier which combines the frequency divided signal to provide an output signal of substantially constant amplitude and having a frequency equal to that of the incoming signal.

Abstract: An FM detection apparatus comprising a frequency dividing means, having a division ratio N, arranged to receive an incoming radio frequency (RF) signal carrying frequency modulation and to frequency divide the RF signal to provide a plurality of frequency divided signals each at the same frequency but mutually phase displaced so that the RF signal is represented by the divided signals in combination, a plurality of FM detectors arranged so that each FM detector receives a different one of the frequency divided signals and provides an output signal corresponding to the frequency modulation carried by the received frequency divided signal, and adding means operative to combine the output signals to provide a demodulated signal corresponding to the modulation carried by the incoming RF signal.

Abstract: A frequency modulation detection arrangement comprises an FM detector and an injection-locked frequency divider arranged for receiving a radio signal and for providing a frequency divided radio signal in response thereto. The FM detector is coupled with the injection-locked frequency divider for receiving the frequency divided radio signal therefrom and for producing a signal indicative of the information content of the modulating wave of the radio signal.

Abstract: An FM detector comprises a frequency divider arranged to frequency divide an input FM signal and a phase sensitive detector coupled to the frequency divider. The detector receives a first frequency divided signal from a first path and receives a second frequency divided signal from a second path. The second path has a phase shift means located therein which is operative to shift the phase of the second frequency divided signal, in dependence on its frequency, relative to the phase of the first frequency divided signal. The phase sensitive detector provides an output signal corresponding to the modulation carried by the input signal.

Abstract: A phase lock loop circuit comprises a variable frequency oscillator having a control input and an output, a divider having an input coupled with the output of the oscillator and an output coupled with the first input of a phase or frequency comparator. The comparator has a second input for a reference frequency (F.sub.REF) and an output coupled with the oscillator control input for providing a signal which is related to the difference in phase or frequency of the signals at the first and second inputs to effect phase locking of the oscillator to the reference signal. A detector provides a switching signal when the control signal falls outside a predetermined range and a switch in the phase lock loop is responsive to the switching signal to open the loop.

Abstract: An adjustable ratio divider comprises a controllable gate connected in series with a divider for passing a clock signal in pulse form whose frequency is to be divided. A means is provided for controlling the gate to subtract a selectable number (including zero) of clock pulses from the clock signal to control the division ratio of the divider.

Abstract: A surface acoustic wave filter arrangement is provided in which both filter and associated driving amplifier are arranged in the same integrated circuit package.

Abstract: This disclosure relates to an electronic circuit which has a controllable impedance. This type of circuit is well suited for application in noise suppression circuits or in signal compression/expansion circuits. The circuit has two stages. The first stage is a voltage to current converter. The second stage is a variable gain current amplifier. The output of the second stage is connected by a feedback loop to an input of the first stage. The circuit has a variable impedance which can be controlled by an external signal. The imput impedance of the circuit is linearly related to the applied control signal.