Patents by Inventor Rodolfo F. Garcia

Rodolfo F. Garcia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6775637
    Abstract: A method and associated apparatus for testing devices outputting source synchronous signals using automated test equipment (“ATE”). An output data signal and an output clock signal from such a source synchronous device under test are delayed using a delay network. The delay provides the time required to deskew path errors and to buffer and distribute the output clock signal. The output data signal appears relatively stable to the ATE by reading the output data signal using the output clock signal.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: August 10, 2004
    Assignee: NPTest, LLC
    Inventor: Rodolfo F. Garcia
  • Publication number: 20030229466
    Abstract: A method and associated apparatus for testing devices outputting source synchronous signals using automated test equipment (“ATE”). An output data signal and an output clock signal from such a source synchronous device under test are delayed using a delay network. The delay provides the time required to deskew path errors and to buffer and distribute the output clock signal. The output data signal appears relatively stable to the ATE by reading the output data signal using the output clock signal.
    Type: Application
    Filed: May 15, 2003
    Publication date: December 11, 2003
    Applicant: Schlumberger Technologies, Inc.
    Inventor: Rodolfo F. Garcia
  • Patent number: 5673275
    Abstract: A test system, for testing circuits, having two operating modes, a normal mode and an accelerated mode. The test system has a first start memory, a second start memory, a first sequence memory, and a second sequence memory. The start memories provide sequence memory addresses for addressing the sequence memories, and the sequence memories provide event sequences in response to sequence memory addresses. If operating in normal mode, the start memories are electronically coupled (switched) to provide a single sequence memory address to both sequence memories. If operating in accelerated mode, the start memories are electronically coupled so that the first start memory provides a first sequence memory address to the first sequence memory and the second start memory provides an independent second sequence memory address to the second sequence memory.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: September 30, 1997
    Assignee: Schlumberger Technology, Inc.
    Inventors: Rodolfo F. Garcia, Egbert Graeve
  • Patent number: 5481550
    Abstract: A Device Under Test ("DUT") is monitored to determine when a test stops due to failure, completion, or otherwise. A series of signal stimulus in the form of a maintain active signal are applied to the DUT after the test has stopped. This protects devices that need continuous functional stimulus while connected to a power source. Upon the resumption of the test, the maintain active signal stimulus is synchronously replaced with an input test signal stimulus.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: January 2, 1996
    Assignee: Schlumberger Technologies, Inc.
    Inventors: Rodolfo F. Garcia, Egbert Graeve