Abstract: A method and system for monitoring the performance of a instruction pipeline is provided. The processor may contain a performance monitor for monitoring for the occurrence of an event within a data processing system. An event to be monitored may be specified through software control, and the occurrence of the specified event is monitored during the execution of an instruction in the execution pipeline of the processor. A particular instruction may be specified to execute within a threshold time for each stage of the instruction pipeline. The specified event may be the completion of a single tagged instruction beyond the specified threshold interval for a stage of the instruction pipeline.

Abstract: A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.

Abstract: A microprocessor including a performance monitor unit is disclosed. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus.

Abstract: The luminance of a phosphor suitable for an alternating current thin-film electroluminescent device is substantially improved according to the present invention by including an alkali halide. The alkali halide included within the bulk of the phosphor material results in providing a significant number of trapping states which trap free electrons within the phosphor material. The addition of the trapping states (added defects) within the bulk tend to control the electrical and optical characteristics of the phosphor material. This reduces asymmetric light output characteristics of traditional phosphor material, reduces asymmetric current movement within the phosphor material, and decreases the influence of the interfaces between the phosphor material and insulating materials resulting in decreased aging and increased brightness.

Abstract: A portable antitheft locking mechanism for a motor vehicle steering wheel and brake pedal, e.g., a J-bar, having plural lighting elements, such as light emitting diodes, which generally indicate the profile of the locking mechanism so that it may be seen in darkness before forcible entry. The J-bar includes an independent source of power, such as a battery, which energizes the lighting elements either when the J-bar engages the vehicle member or when the access lock is secured, or both. The lighting elements provide means to inform the thief of the J-bar during darkness so as to deter his ill-intended efforts and spare the owner of unnecessary physical damage resulting from forcible entry. The J-bar preferably includes contact switch element which closes upon engagement with the steering wheel and/or a microswitch responsive to securement of an access lock on the mechanism to activate the lights thereby to conserve source when not in use.