Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.