Abstract: A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Schottky diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high breakdown voltage required to drive the Schottky diode (22) into conduction is reduced by providing a trigger transistor (24) for prematurely triggering the diode (22). When the base-collector junction of the common emitter configured trigger transistor (24) is driven into avalanche breakdown by the electrostatic discharge, charged carriers (60) are generated, and attracted by the Schottky diode (22). The base (54) of the trigger transistor (24) is biased during normal operations with a supply voltage, and during electrostatic discharges to a higher voltage by an inherent Zener diode (64).

Abstract: A hybrid CMOS-bipolar memory cell for a high speed memory includes a CMOS latch which has two storage nodes (104) and (106) for storing two logic states. The CMOS latch is disposed between a high voltage node (110) and a low voltage node (114). The two nodes are maintained at a predetermined voltage to maintain a static state. A bipolar current drive transistor (120) is provided which is connected to one of the storage nodes (106) to provide a low source impedance for output from the memory cell. A work line (44) is connected to the high voltage node (110) for selection thereof by varying between two predetermined voltages. The cell is written to be selectively discharging either node (104) or (106) to a low voltage node (114) through bipolar transistors (122) and (124). The bipolar transistor (122) and (124) provide high transconductance switches for selectively discharging the storage nodes (104) and (106).

Abstract: A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Shockley diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high breakdown voltage required to drive the Shockley diode (22) into conduction is reduced by providing a trigger transistor (24) for prematurely triggering the diode (22). When the base-collector junction of the common emitter configured trigger transistor (24) is driven into avalanche breakdown by the electrostatic discharge, charged carriers (60) are generated, and attracted by the Shockley diode (22). The base (54) of the trigger transistor (24) is biased during normal operations iwth a supply voltage, and during electrostatic discharges to a higher voltage by an inherent Zener diode (64).

Abstract: The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity checker, a comparator and an SRAM memory call array. The cache memory is cascadable for access to an increased address range and to provide increased memory capacity.

Abstract: A reset circuit for a CMOS memory array is disclosed wherein the voltage supply for the standard six transistor memory cell is replaced by a pair of parallel connected transistors disposed between a fixed voltage source and the memory cell. The transistors are controlled by the reset signal and are complementary in that one is n-channel and the other is p-channel. The n-channel transistor is sized to prevent excess current flow to the memory cells to prevent an excessive charge build up therein for a logical "1" representation. In addition, the n-channel transistor provides a Vtn drop thereacross to prevent current flow in the memory cells during reset.

Abstract: A hybrid ECL memory includes a hybrid memory array 36 which utilizes cross coupled CMOS latches (70). Each CMOS latch (70) is accessed by an ECL decoder (40) and an ECL Word Line driver (42) to read data therefrom. Data is accessed through a bipolar transistor (120) for output to an ECL sense amp. The column select operation is provided by an ECL decoder (50) to select both the Read and the Write operation. The Write operation is provided with emitter coupled logic by pulling up one of the storage nodes in the CMOS latch (70) with a low source impedance PNP transistor (122). Selection is provided by varying the Word Line between two voltages through a low source impedance transistor (78) with the voltages being ECL compatible.

Abstract: A fast write CMOS memory cell includes two CMOS inverters connected in a latched configuration with the first CMOS inverter having a P-channel transistor (98) and an N-channel transistor (102) and the second inverter having a P-channel transistor (90) and an N-channel transistor (96). The output of the first inverter is connected to the input of the second inverter with the output of the second inverter connected to the input of the first inverter through a pass transistor (104). The pass transistor (104) is conductive during the static mode of operation and is nonconductive during the write operation. During write, the input of the first inverter is forced to a predetermined logic state with the pass transistor (104) nonconductive. After write, the pass transistor (104) conducts and reconfigures the latch.

Abstract: The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity checker, a comparator and an SRAM memory cell array. The cache memory is cascadable for access to an increased address range and to provide increased memory capacity.

Abstract: Protection against damage due to electrostatic discharge is provided by the addition of elongate conductor ballast resistor strips (18, 20, 22) formed in series with the transistor device (10). The material forming the conductor strips (18, 20, 22) includes a positive temperature coefficient, thereby offsetting the negative temperature coefficient of the semiconductor material forming the transistor (10). Plural conductor strips are arranged in parallel to reduce the overall resistance to the transistor (10). High current density areas are prevented by providing a plurality of sub-transistors (48) formed in plural individual moats (40-46). The individual current paths reduce the formation of filaments caused by the high concentrations of current in a small area.

Abstract: A multiport random access memory cell includes a current mode latch (68) for storing two logic states and interface circuits for interfacing the input of the latch (68) with multiple input ports and the output of the latch (68) with multiple output ports. The interface circuitry comprises current switches (70-76) for switching current to a current source in the presence of a write select and a row select signal to override the holding current in the current mode latch. The output interface circuitry includes current sensors (78-84) for sensing the logic state in the latch and outputting it to the select output ports in the presence of a row select signal. The current switches and the current sensors utilize current mode logic and with a common current source. The current source is disable in the absence of any row select signal such that power is not drawn by the memory cell in the unselected state.