Patents by Inventor Roland Irsigler

Roland Irsigler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8598716
    Abstract: The present invention provides an apparatus having stacked semiconductor components. Two semiconductor components (21, 26) are arranged such that their contact regions (28, 22) are opposite one another. A contact-connection device (29) forms a short electrical connection between the two contact regions (28, 22). The contact regions (28, 22) are connected to external contact regions (36) of the apparatus via a rewiring (23).
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: December 3, 2013
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Patent number: 8124521
    Abstract: A method of fabricating an electrical contact through a through hole in a substrate, wherein the through hole is at least in part filled with a liquid conductive material and the solidified liquid conductive material provides an electrical contact through the through hole.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: February 28, 2012
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Roland Irsigler, Volker Lehmann, Judith Lehmann, legal representative, Thorsten Meyer, Octavio Trovarelli
  • Patent number: 8106511
    Abstract: A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: January 31, 2012
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Roland Irsigler, Rolf Weis, Detlef Weber
  • Patent number: 8072084
    Abstract: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: December 6, 2011
    Assignee: Qimonda AG
    Inventors: Roland Irsigler, Harry Hedler, Stephan Dobritz
  • Patent number: 8048479
    Abstract: A method for placing material onto a target board by means of a transfer board comprising a plurality of blind holes, the method comprising the steps of immersing the transfer board in a material bath, wherein a first pressure acts on the material bath and a second pressure acts in the blind holes, and wherein the first pressure and the second pressure are substantially equal; generating a pressure difference between the first pressure and the second pressure, so that the blind holes of the transfer board are filled at least partially with the liquid material; extracting the transfer board from the material bath; and positioning the transfer board opposite to the target board, the material being expelled from the blind holes, such that the material touches the target board.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: November 1, 2011
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Roland Irsigler, Volker Lehmann, Judith Lehmann, legal representative
  • Patent number: 8049310
    Abstract: A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the semiconductor substrate. The through silicon conductor is electrical isolated from the semiconductor substrate and includes a conductor bump at one of its ends. Between the inner surface of the through hole and the through silicon conductor a gap is formed. The gap surrounds the through silicon conductor on one side of the semiconductor substrate having the conductor bump, and extends from this side of the substrate into the substrate. The gap is filled with a flexible dielectric material.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: November 1, 2011
    Assignee: Qimonda AG
    Inventors: Andreas Wolter, Harry Hedler, Roland Irsigler
  • Publication number: 20110217812
    Abstract: Fabricating an integrated circuit device includes providing a semiconductor substrate comprising a first surface and a second surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semiconductor substrate. The fabricating further includes forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip, thinning the semiconductor substrate at the second surface after forming the embedding layer, and forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate. Moreover, an integrated circuit device is described.
    Type: Application
    Filed: May 17, 2011
    Publication date: September 8, 2011
    Inventors: Harry Hedler, Roland Irsigler, Andreas Wolter
  • Patent number: 7960843
    Abstract: A chip arrangement includes a logic chip with electric contacts arranged on one side, at least one memory chip arrangement with electrical contacts arranged on at least one side, and a substrate with electrical contacts on both sides of the substrate. The logic chip is attached to the substrate and is electrically conductively coupled to the substrate. The memory chip arrangement is arranged on the logic chip on the side facing the substrate and is electrically conductive coupled to the logic chip. The substrate includes a plurality of electrical connections between the contacts of the one and the other side.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: June 14, 2011
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Roland Irsigler
  • Patent number: 7847415
    Abstract: A multichip module assembly includes a chipset of at least two chips. The chips have active sides, rear sides and chip contacts on their active sides adjacent each other and are embedded in a polymer matrix in a symmetrical manner relating to the top and the bottom surface of the chipset. Chip contacts are electrically connected by through polymer connectors that each extend from a chip contact to a surface of the polymer matrix. A film wiring line is arranged on a side of the polymer matrix for electrical connection of two through polymer connectors of two chips or a through polymer connector with an interconnect element arranged on a side of the polymer matrix.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 7, 2010
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Roland Irsigler
  • Patent number: 7834462
    Abstract: According to one embodiment of the present invention, an electric device includes: a top surface and a bottom surface; a contact hole extending from the top surface through the device to the bottom surface; a conductive sealing element which seals the contact hole at or near the bottom surface; a conductive connection which is coupled to the conductive sealing element and which extends through the contact hole to the top surface; and solder material which is provided on a bottom surface of the conductive sealing element.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: November 16, 2010
    Assignee: Qimonda AG
    Inventors: Stephan Dobritz, Christoph Polaczyk, Roland Irsigler
  • Patent number: 7829380
    Abstract: A method of forming flip chip bumps includes forming a plurality of metallization pads on a die. In another step, a structured layer having pores is formed on the die and metallization pads where the pads on the die are exposed through the pores. In yet another step, the die is transferred to a chamber having a liquid metal bath. In another step, a first pressure is created within the chamber followed by dipping the die in the liquid metal bath. In another step, a second pressure is created within the chamber such that liquid metal fills portions of the pores thereby forming metal pillars connected to the pads.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: November 9, 2010
    Assignee: Qimonda AG
    Inventors: Roland Irsigler, Harry Hedler
  • Publication number: 20100065949
    Abstract: Structures and methods of forming stacked chips are disclosed. In one embodiment, a first chip is disposed over a second chip, a top surface of the first and the second chip includes active circuitry. A first through substrate via is disposed within the first chip, the first through substrate via includes a protruding tip projecting below a bottom surface of the first chip, the bottom surface being opposite the top surface. A second through substrate via is disposed on the second chip, the second through substrate via including an opening, wherein the first protruding tip of the first chip is disposed within the opening of the second chip.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 18, 2010
    Inventors: Andreas Thies, Harry Hedler, Roland Irsigler
  • Publication number: 20100013101
    Abstract: A multichip module assembly includes a chipset of at least two chips. The chips have active sides, rear sides and chip contacts on their active sides adjacent each other and are embedded in a polymer matrix in a symmetrical manner relating to the top and the bottom surface of the chipset. Chip contacts are electrically connected by through polymer connectors that each extend from a chip contact to a surface of the polymer matrix. A film wiring line is arranged on a side of the polymer matrix for electrical connection of two through polymer connectors of two chips or a through polymer connector with an interconnect element arranged on a side of the polymer matrix.
    Type: Application
    Filed: July 18, 2008
    Publication date: January 21, 2010
    Inventors: Harry Hedler, Roland Irsigler
  • Patent number: 7646090
    Abstract: The present invention provides a semiconductor module having: a semiconductor device (10) having a contact device (11) for making electrical contact with a connection device (17; 20) via a rewiring device (15, 15?, 15?); and a carrier device (12, 13, 14) for mechanically coupling the semiconductor device (10) to a connection device (17), the carrier device (12, 13, 14) having a gradient between a first modulus of elasticity at the semiconductor device (10) and a second, higher modulus of elasticity at the connection device (17; 20). The present invention likewise provides a method for producing a semiconductor module.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: January 12, 2010
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20090321959
    Abstract: A chip arrangement includes a logic chip with electric contacts arranged on one side, at least one memory chip arrangement with electrical contacts arranged on at least one side, and a substrate with electrical contacts on both sides of the substrate. The logic chip is attached to the substrate and is electrically conductively coupled to the substrate. The memory chip arrangement is arranged on the logic chip on the side facing the substrate and is electrically conductive coupled to the logic chip. The substrate includes a plurality of electrical connections between the contacts of the one and the other side.
    Type: Application
    Filed: June 16, 2009
    Publication date: December 31, 2009
    Inventors: Harry Hedler, Roland Irsigler
  • Patent number: 7638869
    Abstract: A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: December 29, 2009
    Assignee: Qimonda AG
    Inventors: Roland Irsigler, Steve Wood, Hermann Ruckerbauer, Richard Johannes Luyken, Carsten Niepelt
  • Publication number: 20090243047
    Abstract: A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the semiconductor substrate. The through silicon conductor is electrical isolated from the semiconductor substrate and includes a conductor bump at one of its ends. Between the inner surface of the through hole and the through silicon conductor a gap is formed. The gap surrounds the through silicon conductor on one side of the semiconductor substrate having the conductor bump, and extends from this side of the substrate into the substrate. The gap is filled with a flexible dielectric material.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 1, 2009
    Inventors: Andreas Wolter, Harry Hedler, Roland Irsigler
  • Publication number: 20090218690
    Abstract: A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Inventors: Harry Hedler, Roland Irsigler, Rolf Weis, Detlef Weber
  • Publication number: 20090212420
    Abstract: Fabricating an integrated circuit device includes providing a semiconductor substrate comprising a first surface and a sec-ond surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semi-conductor substrate. The fabricating further includes forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip, thinning the semiconductor substrate at the second surface after forming the embedding layer, and forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate. Moreover, an integrated circuit de-vice is described.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Inventors: Harry Hedler, Roland Irsigler, Andreas Wolter
  • Publication number: 20090072398
    Abstract: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: Qimonda AG
    Inventors: Roland Irsigler, Harry Hedler, Stephan Dobritz