Patents by Inventor Roland Irsigler

Roland Irsigler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7074649
    Abstract: The present invention provides a method for producing an integrated circuit with a rewiring device. In the method, there is provision of a carrier device with defined cutouts, application of at least one integrated circuit upside down to the carrier device such that the defined cutouts of the carrier device are located above at least one connection device of the integrated circuit application of an insulation device to that side of the carrier device which is not covered by the integrated circuit, omitting the at least one connection device in the cutout); application of the patterned rewiring device to the insulation device; application of a patterned solder resist device to the patterned rewiring device; and patterned application of solder balls on sections of the rewiring device which are not covered by the patterned solder resist device. The present invention likewise provides such an apparatus.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: July 11, 2006
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20060091561
    Abstract: The invention relates to an electronic device and a method for producing it having external area contacts and having a rewiring structure and also having a semiconductor chip, which has contact areas, the external area contacts being electrically connected to the contact areas at least by means of the rewiring structure, and the external area contacts and/or the rewiring structure having chemically or galvanically selectively deposited metal.
    Type: Application
    Filed: May 23, 2003
    Publication date: May 4, 2006
    Inventors: Jochen Dangelmaier, Harry Hedler, Roland Irsigler, Stefan Paulus
  • Patent number: 7022549
    Abstract: An integrated circuit, in particular from a chip, a wafer or a hybrid, to a substrate. A package is provided for the integrated circuit, which has a connection side, on which there are provided a plurality of connection regions for connection to the substrate. A corresponding plurality of connection regions are provided on the substrate, and elevated contact regions are provided on the connection regions of the package and/or the connection regions of the substrate. The elevated contact regions include a first group of contact regions and a second group of contact regions. A connection of the package to the substrate is created via the elevated contact regions. The elevated contact regions configured such that the first group of contact regions form a rigid connection and the second group of contact regions form an elastic connection between the package and the substrate. The invention likewise provides a corresponding circuit arrangement.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: April 4, 2006
    Assignee: Infineon Technologies, AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20060043561
    Abstract: The present invention provides an apparatus having stacked semiconductor components. Two semiconductor components (21, 26) are arranged such that their contact regions (28, 22) are opposite one another. A contact-connection device (29) forms a short electrical connection between the two contact regions (28, 22). The contact regions (28, 22) are connected to external contact regions (36) of the apparatus via a rewiring (23).
    Type: Application
    Filed: August 24, 2005
    Publication date: March 2, 2006
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20060043573
    Abstract: A semiconductor device comprises at least one first semiconductor component being located in a first plane and comprising an active area which has a first contact region and at least one second semiconductor component being located in a second plane and comprising a second active area which has a second contact region. The second semiconductor component is located at a distance vertically to the first semiconductor component and is orientated relative to the first semiconductor component, so that the first active area faces away from the second semiconductor component and the second active area faces away from the first semiconductor component. An adhesive layer is arranged between the first and the second semiconductor components and a frame region adjoins laterally the first semiconductor component and the second semiconductor component on at least one side. The frame region comprises a first surface and a second surface which is located opposite to the second surface.
    Type: Application
    Filed: August 24, 2005
    Publication date: March 2, 2006
    Inventors: Harry Hedler, Roland Irsigler
  • Patent number: 6979591
    Abstract: A method for connecting a first integrated circuit having an elevated contact area lying on an elastic elevation on a main area thereof and a second integrated circuit having a corresponding non-elevated contact area on a main area thereof includes applying a liquid adhesive between the first and second main areas; aligning the first and second main areas so that the elevated contact area is opposite the corresponding non-elevated contact area; and curing the adhesive, thereby firmly connecting the first and second integrated circuits.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: December 27, 2005
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Jens Pohl
  • Publication number: 20050282410
    Abstract: The present invention relates to an elastic contact-connecting device. An elastic elevation 3 is applied to a carrier area 2 of a carrier 1. The elastic elevation 3 has a first oblique area 4, a second ramp 5 and a roof area 6. The first oblique area 4 has a lesser inclination (30) with regard to the carrier area 2 than the second oblique area 5. A contact region 20 is applied to the roof area 6 of the elastic elevation. The contact region 20 is connected to other structures 12 on the carrier 1 via a conductor track 10. For this purpose, the conductor track 10 is guided over the first oblique area 4. If a mating contact is pressed onto the contact region 20, the elastic elevation yields, but presses against the mating contact on account of its elastic property and thus enables a reliable contact. In this case, essentially only the second oblique area 5 is deformed; the first oblique area 4 and the conductor track 10 applied thereto are not subjected to any mechanical stress.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 22, 2005
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer, Andreas Wolter
  • Publication number: 20050250304
    Abstract: A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.
    Type: Application
    Filed: August 15, 2003
    Publication date: November 10, 2005
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez
  • Patent number: 6919232
    Abstract: A process for producing a semiconductor chip having contact elements protruding on one chip side within the context of wafer level packaging, the chip side provided with the contact elements being coated with a covering compound forming a protective layer, from which the protruding contact element project.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: July 19, 2005
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Barbara Vasquez
  • Patent number: 6897088
    Abstract: A method of connecting a first and second circuit device includes providing a first circuit device having a first main area and a second circuit device having a second and a third main area. A spacer device is disposed on one of the first and second circuit devices to ensure a predetermined spacing between the first and second circuit devices. An adhesive is applied to at least one of the first main area and the second main area and the first and second circuit devices are aligned and joined. The adhesive is then cured.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: May 24, 2005
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Jens Pohl
  • Publication number: 20050077632
    Abstract: A method for producing a multi-chip module having application of at least one contact elevation onto a substrate, application and patterning of a rewiring device onto the substrate and the at least one contact elevation with provision of a contact device on the at least one contact elevation, application of a semiconductor chip onto the substrate with electrical contact-connection of the rewiring device; application of an encapsulating device that is not electrically conductive onto the semiconductor chip, the substrate, the rewiring device and the at least one contact elevation, the contact device on the at least one contact elevation at least touching a first surface of the encapsulating device; and repetition at least once of at least the first two steps, the first surface of the encapsulating device serving as a substrate and the correspondingly produced rewiring device making electrical contact with the contact device of the at least one contact elevation of the underlying plane.
    Type: Application
    Filed: September 29, 2004
    Publication date: April 14, 2005
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Harry Hedler, Roland Irsigler
  • Publication number: 20050067689
    Abstract: The present invention provides a semiconductor module having: at least one semiconductor device (10); a rigid covering device (14) over the at least one semiconductor device (10) for protecting and dissipating heat from the at least one semiconductor device (10); and a carrier device (17), which has a connection device (19), for receiving the semiconductor device (10) and the covering device (14), the at least one semiconductor device (10) being electrically coupled to the connection device (19) by means of a flexible contact device (11) via the carrier device (17) and being mechanically coupled to the covering device (14) via a contact device (15, 16). The present invention likewise provides a method for producing a semiconductor module.
    Type: Application
    Filed: July 28, 2004
    Publication date: March 31, 2005
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20050048676
    Abstract: A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer which is to be applied locally; a rewiring extending between the local covering layers is created; the local covering layers are removed; and the laser-induced correction is carried out by means of the open laser vias.
    Type: Application
    Filed: May 13, 2002
    Publication date: March 3, 2005
    Inventors: Harry Hedler, Roland Irsigler, Barbara Vasquez
  • Patent number: 6861291
    Abstract: A contact connection between a semiconductor chip and a substrate has a conductive adhesive extending between each contact of the chip and the substrate. The conductive adhesive includes a matrix component, a filler component, a hardener component and at least one decomposable component so that after curing at a curing temperature T1, the adhesive can be decomposed either by applying thermal energy at a temperature T2>T1 or by radiation so that the two contact surfaces can be separated smoothly. After separation the purposes of replacing a defective semiconductor chip, a second chip can be mechanically connected by applying the adhesive and curing it.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: March 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Barbara Vasquez, Roland Irsigler
  • Patent number: 6845554
    Abstract: The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: January 25, 2005
    Assignee: Infineon Technologies AG
    Inventors: Gerd Frankowsky, Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez
  • Publication number: 20050014394
    Abstract: A contact-connection device for electronic circuit units includes an adapter board, at least one elastic element arranged on the adapter board, conductor tracks arranged on the at least one elastic element and the adapter board, conductor track connecting elements deposited on the adapter board and electrically connected to the conductor tracks, and contact-connection elements deposited on the at least one elastic element and electrically connected to the conductor tracks, the contact-connection elements contact-connecting circuit unit connecting elements of the circuit units in an elastically pressing-on fashion.
    Type: Application
    Filed: May 28, 2004
    Publication date: January 20, 2005
    Applicant: INFINEON TECHNOLOGIES
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer, Peter Weitz
  • Publication number: 20050014309
    Abstract: The present invention provides a method for producing an integrated circuit with a rewiring device. In the method, there is provision of a carrier device with defined cutouts, application of at least one integrated circuit upside down to the carrier device such that the defined cutouts of the carrier device are located above at least one connection device of the integrated circuit application of an insulation device to that side of the carrier device which is not covered by the integrated circuit, omitting the at least one connection device in the cutout); application of the patterned rewiring device to the insulation device; application of a patterned solder resist device to the patterned rewiring device; and patterned application of solder balls on sections of the rewiring device which are not covered by the patterned solder resist device. The present invention likewise provides such an apparatus.
    Type: Application
    Filed: November 26, 2003
    Publication date: January 20, 2005
    Applicant: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20040217483
    Abstract: A semiconductor device has a semiconductor substrate, at least a first and second rewiring device on a first surface of the semiconductor substrate for the provision of an electrical contact-connection of the semiconductor substrate, and a tapering, continuous opening from a first surface to a second, opposite surface of the semiconductor substrate. At least a third and fourth rewiring device is disposed on the second surface of the semiconductor substrate and a patterned metallization on the side areas of the opening for the separate contact-connection of the first and at least the second rewiring device.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 4, 2004
    Applicant: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20040191958
    Abstract: An integrated circuit, in particular from a chip, a wafer or a hybrid, to a substrate. A package is provided for the integrated circuit, which has a connection side, on which there are provided a plurality of connection regions for connection to the substrate. A corresponding plurality of connection regions are provided on the substrate, and elevated contact regions are provided on the connection regions of the package and/or the connection regions of the substrate. The elevated contact regions include a first group of contact regions and a second group of contact regions. A connection of the package to the substrate is created via the elevated contact regions. The elevated contact regions configured such that the first group of contact regions form a rigid connection and the second group of contact regions form an elastic connection between the package and the substrate. The invention likewise provides a corresponding circuit arrangement.
    Type: Application
    Filed: December 30, 2003
    Publication date: September 30, 2004
    Applicant: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Patent number: 6714418
    Abstract: An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: March 30, 2004
    Assignee: Infineon Technologies AG
    Inventors: Gerd Frankowsky, Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez