Patents by Inventor Roland Schuetz

Roland Schuetz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170333168
    Abstract: A holding device for a dental blank for clamping the holding device in a power tool, to machine the blank by material removal, has at least one recess to accommodate the blank, and the wall of the recess has a lengthwise groove, in which a fixation element can be moved towards the center of the recess by adjustment elements. A blank arrangement comprising a holding device, as well as one cylindrical or two semi-cylindrical dental blanks, is clamped in the holding device by the adjustment elements and the fixation element. The subject innovation also relates to a method for the height-appropriate positioning of a blank in the holding device according to the subject innovation using a template, and to a method for the production of a dental sintered molded part involving the sintering of the entire dental blank with the milled-out parts contained therein.
    Type: Application
    Filed: March 9, 2016
    Publication date: November 23, 2017
    Inventor: Roland Schuetz
  • Publication number: 20170065381
    Abstract: A holding device for a dental blank for clamping the holding device in a power tool, to machine the blank by material removal, has at least one recess to accommodate the blank, and the wall of the recess has a lengthwise groove, in which a fixation element can be moved towards the center of the recess by adjustment elements. A blank arrangement comprising a holding device, as well as one cylindrical or two semi-cylindrical dental blanks, is clamped in the holding device by the adjustment elements and the fixation element. The subject innovation also relates to a method for the height-appropriate positioning of a blank in the holding device according to the subject innovation using a template, and to a method for the production of a dental sintered molded part involving the sintering of the entire dental blank with the milled-out parts contained therein.
    Type: Application
    Filed: March 9, 2016
    Publication date: March 9, 2017
    Inventor: Roland Schuetz
  • Patent number: 9117685
    Abstract: Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: August 25, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Roland Schuetz
  • Patent number: 9009423
    Abstract: A memory system has a controller. A plurality of memory devices are serially interconnected with the controller via an n-bit data interface. The memory system is configurable in a first mode to communicate each read and write operation between the controller and the memory devices using all n bits of the data interface. The memory system is configurable in a second mode to concurrently: communicate data associated with a first operation between the controller and a first target memory device using only m bits of the data interface, where m is less than n; and communicate data associated with a second operation between the controller and a second target memory device using the remaining n-m bits of the data interface. A memory device, a memory controller, and a method are also described.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: April 14, 2015
    Assignee: NovaChips Canada Inc.
    Inventor: Roland Schuetz
  • Publication number: 20140325178
    Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.
    Type: Application
    Filed: July 14, 2014
    Publication date: October 30, 2014
    Inventors: Steven PRZYBYLSKI, Roland SCHUETZ, HakJune OH, Hong Beom PYEON
  • Patent number: 8812768
    Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: August 19, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Steven Przybylski, Roland Schuetz, HakJune Oh, Hong Beom Pyeon
  • Patent number: 8767430
    Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: July 1, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Peter Gillingham, Roland Schuetz
  • Publication number: 20140141566
    Abstract: A semiconductor device has a substrate having a first plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice is disposed on the substrate. Each die of the plurality of dice has a first plurality of die bonding pads arranged along at least one first edge thereof. A plurality of bonding pillars extends substantially vertically from the substrate bonding pads. Each bonding pillar electrically connects one of the first plurality of substrate bonding pads to a corresponding one of the first plurality of die bonding pads. A method of assembling a semiconductor device is also described.
    Type: Application
    Filed: January 24, 2014
    Publication date: May 22, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Roland SCHUETZ
  • Publication number: 20140097891
    Abstract: Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.
    Type: Application
    Filed: December 10, 2013
    Publication date: April 10, 2014
    Inventor: Roland Schuetz
  • Patent number: 8675425
    Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 18, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventors: Roland Schuetz, Jin-Ki Kim
  • Patent number: 8637984
    Abstract: A semiconductor device has a substrate having a first plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice is disposed on the substrate. Each die of the plurality of dice has a first plurality of die bonding pads arranged along at least one first edge thereof. A plurality of bonding pillars extends substantially vertically from the substrate bonding pads. Each bonding pillar electrically connects one of the first plurality of substrate bonding pads to a corresponding one of the first plurality of die bonding pads. A method of assembling a semiconductor device is also described.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: January 28, 2014
    Assignee: Mosaid Technologies Incorporated
    Inventor: Roland Schuetz
  • Patent number: 8604593
    Abstract: Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: December 10, 2013
    Assignee: Mosaid Technologies Incorporated
    Inventor: Roland Schuetz
  • Publication number: 20130322173
    Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
    Type: Application
    Filed: August 2, 2013
    Publication date: December 5, 2013
    Applicant: Mosaid Technologies Incorporated
    Inventors: Peter Gillingham, Roland Schuetz
  • Patent number: 8587111
    Abstract: A semiconductor device includes a substrate having a plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice are stacked on the bonding surface of the substrate to form a die stack. Each die has a plurality of die bonding pads arranged along at least one bonding edge thereof. The remaining edges of each die are non-bonding edges. A plurality of bonding wires each electrically connects one of the die bonding pads to one of the substrate bonding pads. At least one thermally conductive layer is disposed between two adjacent semiconductor dice. At least one thermally conductive lateral portion is in thermal contact with the at least one layer of thermally conductive material. Each thermally conductive lateral portion is arranged along a non-bonding edge of the die stack.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: November 19, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventor: Roland Schuetz
  • Patent number: 8503211
    Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: August 6, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventors: Peter Gillingham, Roland Schuetz
  • Patent number: 8443233
    Abstract: A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the selected device while in the recovery mode of operation; if the attempt is successful, selecting a next device in the configuration of series-connected semiconductor devices and repeating the sending and the attempting to elicit; and if the attempt is unsuccessful, concluding that the selected device is an anomalous device.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: May 14, 2013
    Assignee: Mosaid Technologies Incorporated
    Inventor: Roland Schuetz
  • Publication number: 20130094271
    Abstract: A system comprising a plurality of memory devices coupled by a common bus to a controller has a single serially coupled enable signal per channel. Each memory device or chip comprises a serial enable input and enable output and a register for storing a device identifier, e.g., chip ID. The memory devices are serially coupled by a serial enable link, for assertion of a single enable signal to all devices. This parallel data and serial enable configuration provides reduced per-channel pin count, relative to conventional systems that require a unique enable signal for each device. In operation, commands on the common bus targeting an individual device are asserted by adding an address field comprising a device identifier to each command string, preferably in an initial identification cycle of the command. Methods are also disclosed for initializing the system, comprising assigning device identifiers and obtaining a device count, prior to normal operation.
    Type: Application
    Filed: August 17, 2012
    Publication date: April 18, 2013
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Roland Schuetz
  • Publication number: 20130086334
    Abstract: A memory system has a controller. A plurality of memory devices are serially interconnected with the controller via an n-bit data interface. The memory system is configurable in a first mode to communicate each read and write operation between the controller and the memory devices using all n bits of the data interface. The memory system is configurable in a second mode to concurrently: communicate data associated with a first operation between the controller and a first target memory device using only m bits of the data interface, where m is less than n; and communicate data associated with a second operation between the controller and a second target memory device using the remaining n-m bits of the data interface. A memory device, a memory controller, and a method are also described.
    Type: Application
    Filed: April 26, 2011
    Publication date: April 4, 2013
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Roland Schuetz
  • Patent number: 8406070
    Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: March 26, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventors: Roland Schuetz, Jin-Ki Kim
  • Publication number: 20120001314
    Abstract: A semiconductor device includes a substrate having a plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice are stacked on the bonding surface of the substrate to form a die stack. Each die has a plurality of die bonding pads arranged along at least one bonding edge thereof. The remaining edges of each die are non-bonding edges. A plurality of bonding wires each electrically connects one of the die bonding pads to one of the substrate bonding pads. At least one thermally conductive layer is disposed between two adjacent semiconductor dice. At least one thermally conductive lateral portion is in thermal contact with the at least one layer of thermally conductive material. Each thermally conductive lateral portion is arranged along a non-bonding edge of the die stack.
    Type: Application
    Filed: April 20, 2011
    Publication date: January 5, 2012
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Roland SCHUETZ