Patents by Inventor Roland Thewes

Roland Thewes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9576642
    Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array,—at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: February 21, 2017
    Assignee: Soitec
    Inventors: Roland Thewes, Richard Ferrant
  • Patent number: 9478275
    Abstract: The disclosure relates to semiconductor memory devices and related methods. A semiconductor memory device comprises: a single-ended sense amplifier circuit for reading data sensed from selected memory cells in a memory array, the sense amplifier having a first node used to feed in a reference signal, a second node coupled to a bit line, and sense transistors responsible for amplifying the content of a selected memory cell during a sense operation, a reference circuit having replica transistors of the sense transistors and further comprising a regulation network designed so that each replica transistor operates in a stable operating point, and wherein the regulation network generates a control voltage that is applied to the sense amplifier circuit.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: October 25, 2016
    Assignee: SOITEC
    Inventor: Roland Thewes
  • Patent number: 9390771
    Abstract: A circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, a decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 12, 2016
    Assignee: Soitec
    Inventors: Richard Ferrant, Roland Thewes
  • Publication number: 20160086652
    Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array, at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.
    Type: Application
    Filed: April 24, 2014
    Publication date: March 24, 2016
    Inventors: Roland Thewes, Richard Ferrant
  • Patent number: 9251871
    Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: February 2, 2016
    Assignee: Soitec
    Inventors: Richard Ferrant, Joerg Vollrath, Roland Thewes, Wolfgang Hoenlein, Hofmann Franz, Gerhard Enders
  • Publication number: 20150279448
    Abstract: The disclosure relates to semiconductor memory devices and related methods. A semiconductor memory device comprises: a single-ended sense amplifier circuit for reading data sensed from selected memory cells in a memory array, the sense amplifier having a first node used to feed in a reference signal, a second node coupled to a bit line, and sense transistors responsible for amplifying the content of a selected memory cell during a sense operation, a reference circuit having replica transistors of the sense transistors and further comprising a regulation network designed so that each replica transistor operates in a stable operating point, and wherein the regulation network generates a control voltage that is applied to the sense amplifier circuit.
    Type: Application
    Filed: October 10, 2013
    Publication date: October 1, 2015
    Inventor: Roland Thewes
  • Patent number: 9135964
    Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: September 15, 2015
    Assignee: Soitec
    Inventors: Richard Ferrant, Roland Thewes
  • Patent number: 9111593
    Abstract: The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: August 18, 2015
    Assignee: Soitec
    Inventors: Richard Ferrant, Roland Thewes
  • Patent number: 8953399
    Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-down transistors.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 10, 2015
    Assignee: Soitech
    Inventors: Richard Ferrant, Roland Thewes
  • Publication number: 20140376318
    Abstract: a circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.
    Type: Application
    Filed: January 16, 2013
    Publication date: December 25, 2014
    Inventors: Richard Ferrant, Roland Thewes
  • Publication number: 20140321225
    Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.
    Type: Application
    Filed: November 14, 2012
    Publication date: October 30, 2014
    Applicant: SOITEC
    Inventors: Richard Ferrant, Joerg Vollrath, Roland Thewes, Wolfgang Hoenlein, Hofmann Franz, Gerhard Enders
  • Patent number: 8702921
    Abstract: A biosensor array having a substrate, a plurality of biosensor zones arranged on the substrate, each of which has a first terminal and a second terminal, at least one drive line and at least one detection line, the at least one drive line being electrically insulated from the at least one detection line. In each case the first terminal of each biosensor zone is coupled to precisely one of the at least one drive line and the second terminal of each biosensor zone is coupled to precisely one of the at least one detection line, and at least one of the at least one drive line and at least one of the at least one detection line is coupled to at least two of the biosensor zones.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: April 22, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Alexander Frey, Franz Hofmann, Birgit Holzapfl, Christian Paulus, Meinrad Schienle, Roland Thewes
  • Publication number: 20120275252
    Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicant: SOITEC
    Inventors: Richard Ferrant, Roland Thewes
  • Publication number: 20120275254
    Abstract: The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicant: SOITEC
    Inventors: Richard Ferrant, Roland Thewes
  • Publication number: 20120275253
    Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-up transistors.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicant: SOITEC
    Inventors: Richard Ferrant, Roland Thewes
  • Patent number: 8262875
    Abstract: A sensor arrangement including a control circuit is disclosed. In at least one embodiment, at least one sensor electrode can be charged and/or discharged therewith and a comparator unit for the comparison of a provided voltage for the at least one electrode with a reference voltage. A duration necessary for the charging/discharging of the at least one sensor electrode is determined, whereby, from the determined duration, it is determined whether a sensor event, in the form of a hybridization between trap molecules and the particles for recording, has occurred.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: September 11, 2012
    Assignee: Siemens Aktiengesellschaft
    Inventors: Christian Paulus, Meinrad Schienle, Claudio Stagni Degli Esposti, Roland Thewes
  • Patent number: 8183906
    Abstract: The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Ralf Brederlow
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 7944725
    Abstract: A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically decoupled from the read amplifier, and wherein the semiconductor memory controls the first switching element so that the first switching element, when reading out and/or refreshing any memory cell connected to the bit line, temporarily electrically decouples at least the partial section of the bit line from the read amplifier.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: May 17, 2011
    Assignee: Qimonda AG
    Inventors: Roland Thewes, Michael Otto, Helmut Schneider
  • Patent number: 7936628
    Abstract: A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier strips between which the remaining read amplifier strips and the memory cell fields are arranged, wherein adjacent to at least one of the outer read amplifier strips, a reference circuit field is arranged, which has reference lines and reference circuit elements connected thereto, and wherein the reference lines are shorter than the bit lines of the memory cell fields.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: May 3, 2011
    Assignee: Qimonda AG
    Inventors: Helmut Schneider, Roland Thewes