Patents by Inventor Romain LALLEMENT
Romain LALLEMENT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230280644Abstract: Embodiments of present invention provide a method of forming an extreme ultraviolet (EUV) mask. The method includes subliming a radiation-sensitive material onto a surface of an EUV blank substrate; exposing the radiation-sensitive material to an ionizing radiation to form an EUV mask pattern; and removing a portion of the radiation-sensitive material from the surface of the EUV blank substrate where the portion of the radiation-sensitive material is unexposed to the ionizing radiation. An EUV mask made therefrom, and the related radiation-sensitive material are also provided.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Inventors: Dario Goldfarb, Martin Burkhardt, Romain Lallement, Luciana Meli
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Patent number: 11569132Abstract: Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.Type: GrantFiled: December 30, 2020Date of Patent: January 31, 2023Assignee: International Business Machines CorporationInventors: Romain Lallement, Indira Seshadri, Ruqiang Bao
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Patent number: 11177132Abstract: Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.Type: GrantFiled: July 3, 2019Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junli Wang, Romain Lallement, Ardasheir Rahman, Liying Jiang, Brent A. Anderson
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Publication number: 20210118743Abstract: Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.Type: ApplicationFiled: December 30, 2020Publication date: April 22, 2021Inventors: Romain Lallement, Indira Seshadri, Ruqiang Bao
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Patent number: 10903124Abstract: Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.Type: GrantFiled: April 30, 2019Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: Romain Lallement, Indira Seshadri, Ruqiang Bao
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Publication number: 20210005459Abstract: Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Inventors: Junli Wang, Romain Lallement, Ardasheir Rahman, Liying Jiang, Brent A. Anderson
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Patent number: 10832919Abstract: A method for modeling planarization performance of a given material includes patterning a first photoresist layer over a first material deposited over a substrate. The method also includes etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising two or more different design macros in two or more different regions. The method further includes coating the given material over the patterned topography of the first material, patterning a second photoresist layer over the given material, measuring the critical dimension of a metrology feature in each of the two or more different regions, and utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material.Type: GrantFiled: April 11, 2018Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Romain Lallement, Stuart A. Sieg
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Publication number: 20200350212Abstract: Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.Type: ApplicationFiled: April 30, 2019Publication date: November 5, 2020Inventors: Romain Lallement, Indira Seshadri, Ruqiang Bao
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Patent number: 10642950Abstract: Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.Type: GrantFiled: February 6, 2018Date of Patent: May 5, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Romain Lallement, Stuart A. Sieg
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Publication number: 20200118828Abstract: A planarization method for maintaining a substantially planar surface is presented. The method includes forming an organic planarization layer (OPL) over active devices, incorporating a dissolving factor to a predetermined depth within the OPL, and triggering the dissolving factor with an enabler to reduce a thickness of the OPL to a boundary defined by the predetermined depth of the dissolving factor.Type: ApplicationFiled: October 11, 2018Publication date: April 16, 2020Inventor: Romain Lallement
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Patent number: 10514605Abstract: The present invention provides a resist multilayer film-attached substrate, including a substrate and a resist multilayer film formed on the substrate, in which the resist multilayer film has an organic resist underlayer film difficultly soluble in ammonia hydrogen peroxide water, an organic film soluble in ammonia hydrogen peroxide water, a silicon-containing resist middle layer film, and a resist upper layer film laminated on the substrate in the stated order. There can be provided a resist multilayer film-attached substrate that enables a silicon residue modified by dry etching to be easily removed in a wet manner with a removing liquid harmless to a semiconductor apparatus substrate and an organic resist underlayer film required in the patterning process, for example, an ammonia aqueous solution containing hydrogen peroxide called SC1, which is commonly used in the semiconductor manufacturing process.Type: GrantFiled: July 24, 2018Date of Patent: December 24, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SHIN-ETSU CHEMICAL CO., LTD.Inventors: Seiichiro Tachibana, Tsutomu Ogihara, Hiroko Nagai, Romain Lallement, Karen E. Petrillo
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Patent number: 10475904Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess.Type: GrantFiled: January 11, 2018Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Junli Wang, Muthumanickam Sankarapandian
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Publication number: 20190318935Abstract: A method for modeling planarization performance of a given material includes patterning a first photoresist layer over a first material deposited over a substrate. The method also includes etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising two or more different design macros in two or more different regions. The method further includes coating the given material over the patterned topography of the first material, patterning a second photoresist layer over the given material, measuring the critical dimension of a metrology feature in each of the two or more different regions, and utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material.Type: ApplicationFiled: April 11, 2018Publication date: October 17, 2019Inventors: Romain Lallement, Stuart A. Sieg
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Publication number: 20190243927Abstract: Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.Type: ApplicationFiled: February 6, 2018Publication date: August 8, 2019Inventors: Romain Lallement, Stuart A. Sieg
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Patent number: 10354922Abstract: Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.Type: GrantFiled: December 27, 2017Date of Patent: July 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekmini Anuja De Silva, Indira Seshadri, Romain Lallement, Nelson Felix
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Publication number: 20190214484Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Junli Wang, Muthumanickam Sankarapandian
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Publication number: 20190198398Abstract: Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.Type: ApplicationFiled: December 27, 2017Publication date: June 27, 2019Inventors: Ekmini Anuja De Silva, Indira Seshadri, Romain Lallement, Nelson Felix
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Publication number: 20190041753Abstract: The present invention provides a resist multilayer film-attached substrate, including a substrate and a resist multilayer film formed on the substrate, in which the resist multilayer film has an organic resist underlayer film difficultly soluble in ammonia hydrogen peroxide water, an organic film soluble in ammonia hydrogen peroxide water, a silicon-containing resist middle layer film, and a resist upper layer film laminated on the substrate in the stated order. There can be provided a resist multilayer film-attached substrate that enables a silicon residue modified by dry etching to be easily removed in a wet manner with a removing liquid harmless to a semiconductor apparatus substrate and an organic resist underlayer film required in the patterning process, for example, an ammonia aqueous solution containing hydrogen peroxide called SC1, which is commonly used in the semiconductor manufacturing process.Type: ApplicationFiled: July 24, 2018Publication date: February 7, 2019Applicants: SHIN-ETSU CHEMICAL CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Seiichiro TACHIBANA, Tsutomu OGIHARA, Hiroko NAGAI, Romain LALLEMENT, Karen E. PETRILLO