Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor component configured to host a 2DEG or a 2DHG; a superconductor component for inducing superconductivity in a channel of the semiconductor component; and a set of depletion gates. The superconductor component comprises a grounded strip of superconductor. The depletion gates comprise a first outer gate for defining a first outer segment; a second outer gate for defining a second outer segment, and an inner gate for defining an inner segment of the channel. The device further comprises a first junction comprising a space between the first outer gate and the inner gate, and a helper gate for gating the first space; and a second junction comprising a space between the second outer gate and the inner gate, and a helper gate for gating the second space. The helper gates are operable to connect the channel to leads.

Abstract: A method for use with a topological quantum computing device is provided. The method may include setting a plurality of device parameters for a qubit architecture including a plurality of Majorana zero modes (MZMs). The method may further include calibrating the plurality of device parameters at least in part by determining whether the plurality of MZMs exhibit ground state degeneracy. When the plurality of MZMs are determined to not exhibit ground state degeneracy, calibrating the plurality of device parameters may further include modifying one or more device parameters of the plurality of device parameters. When the plurality of MZMs are determined to exhibit ground state degeneracy, the method may further include modifying one or more parameters of a measurement device coupled to the qubit architecture.

Abstract: A superconductor-semiconductor device is provided, including a hybrid superconductor-semiconductor wire. The superconductor-semiconductor device may further include a hybrid localization length (LL) measurement device including a plurality of contact gates located above the hybrid superconductor-semiconductor wire in a thickness direction. The hybrid LL measurement device may further include a conductance sensor electrically coupled to the plurality of contact gates.

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor layer and a superconductor layer. The superconductor layer is arranged over an edge of the semiconductor layer so as to enable energy level hybridisation between the semiconductor layer and the superconductor layer. The semiconductor layer is arranged in a sandwich structure between first and second insulating layers, each insulating layer being in contact with a respective opposed face of the semiconductor layer. This configuration may allow for good control over the geometry of the semiconductor layer and may improve tolerance to manufacturing variations. The device may be useful in a quantum computer. Also provided is a method of manufacturing the device, and a method of inducing topological behaviour in the device.

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a barrier between the superconductor and the semiconductor. The device is configured to enable energy level hybridisation between the semiconductor and the superconductor. The barrier is configured to increase a topological gap of the device. The barrier allows for control over the degree of hybridisation between the semiconductor and the superconductor. Further aspects provide a quantum computer comprising the device, a method of manufacturing the device, and a method of inducing topological behaviour in the device.

Abstract: Topological superconductor devices with gates formed in two gate layers are described. A topological superconductor device includes a superconducting wire having a first junction near a first end of the superconducting wire and a second junction near a second end, opposite to the first end. The topological superconductor device further includes: (1) a first side-plunger gate and a second-side plunger gate formed in a first gate layer of the topological superconductor device, (2) a middle-plunger gate formed in the first gate layer of the topological superconductor device, (3) a first cutter gate formed in a second layer, different from the first layer, of the topological superconductor device, and (4) a second cutter gate formed in the second layer of the topological superconductor device. The plunger gates are operable to tune respective sections of the superconducting wire and the cutter gates are operable to open and close the respective junctions.

Abstract: Quantum devices formed from a single superconducting wire having a configurable ground connection are described. An example quantum device, configurable to be grounded, comprises a single superconducting wire having at least a first section and a second section, each of which is configurable to be in a topological phase and at least a third section configurable to be in a trivial phase. The quantum device further comprises semiconducting regions formed adjacent to the single superconducting wire, where the single superconducting wire is configurable to store quantum information in at least four Majorana zero modes (MZMs). The semiconducting regions formed adjacent to the single superconducting wire may be used to measure quantum information stored in the at least four MZMs.

Abstract: Quantum devices with chains of quantum dots for controlling tunable couplings between Majorana zero modes (MZMs) are described. Methods for controlling tunable couplings between MZMs using such chains of quantum dots are also described. An example quantum device comprises at least one superconducting island configurable to support at least one pair of Majorana zero modes (MZMs). The quantum device may further include a region adjacent to at least one MZM of the at least one pair of MZMs, where the region is configurable to realize a chain of quantum dots for controlling a tunable coupling between the at least one MZM of the at least one pair of MZMs and another MZM.

Abstract: Quantum devices with two-sided or single-sided dual-purpose Majorana zero mode (MZM) junctions are described. An example quantum device comprises at least one superconducting island configurable to support at least one pair of Majorana zero modes (MZMs). The quantum device further includes a first conductor configurable to be coupled with at least one MZM of the at least one pair of MZMs, where the first conductor is configurable to be in at least one of a grounded state or a Coulomb blockade state. The quantum device further includes a second conductor configurable to be coupled with the at least one MZM of the at least one pair of MZMs, where the second conductor is configurable to be in at least one of a grounded state or a Coulomb blockade state.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: A method for use with a topological quantum computing device is provided. The method may include setting a plurality of device parameters for a qubit architecture including a plurality of Majorana zero modes (MZMs). The method may further include calibrating the plurality of device parameters at least in part by determining whether the plurality of MZMs exhibit ground state degeneracy. When the plurality of MZMs are determined to not exhibit ground state degeneracy, calibrating the plurality of device parameters may further include modifying one or more device parameters of the plurality of device parameters. When the plurality of MZMs are determined to exhibit ground state degeneracy, the method may further include modifying one or more parameters of a measurement device coupled to the qubit architecture.

Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor layer and a superconductor layer. The superconductor layer is arranged over an edge of the semiconductor layer so as to enable energy level hybridisation between the semiconductor layer and the superconductor layer. The semiconductor layer is arranged in a sandwich structure between first and second insulating layers, each insulating layer being in contact with a respective opposed face of the semiconductor layer. This configuration may allow for good control over the geometry of the semiconductor layer and may improve tolerance to manufacturing variations. The device may be useful in a quantum computer. Also provided is a method of manufacturing the device, and a method of inducing topological behaviour in the device.

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a barrier between the superconductor and the semiconductor. The device is configured to enable energy level hybridisation between the semiconductor and the superconductor. The barrier is configured to increase a topological gap of the device. The barrier allows for control over the degree of hybridisation between the semiconductor and the superconductor. Further aspects provide a quantum computer comprising the device, a method of manufacturing the device, and a method of inducing topological behaviour in the device.

Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.