Patents by Inventor Ronald A. Sartschev

Ronald A. Sartschev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11514958
    Abstract: Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: November 29, 2022
    Assignee: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Jan Paul Anthonie van der Wagt, Nathan Nary, Grady Borders
  • Publication number: 20220044715
    Abstract: Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 10, 2022
    Applicant: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Jan Paul Anthonie van der Wagt, Nathan Nary, Grady Borders
  • Patent number: 9397670
    Abstract: An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: July 19, 2016
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Jeffrey Wade Sanders, Thomas Aquinas Repucci, Ronald A. Sartschev
  • Patent number: 9279857
    Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: March 8, 2016
    Assignee: Teradyne, Inc.
    Inventors: Howard Lin, Corbin L. Champion, Jan Paul Anthonie van der Wagt, Ronald A. Sartschev
  • Patent number: 9244126
    Abstract: A test technique that may be implemented in an automated test system for testing semiconductor devices. The test technique may enable the fast detection of a signal transition, such as an edge, within a waveform and the timing of that event. Circuitry within a digital instrument that can be quickly and flexibly programmed may, at least in part, implement the test technique. That circuitry may be simply programmed with testing parameters, such that application of the technique may lead to faster test development and faster times. In operation, that circuitry receives parameters specifying parameters of a window over a waveform in which samples of the waveform will be taken to detect the signal transition. The circuitry may convert these parameters into control signals for other components in the test system, such as an edge generator or pin electronics, to take a programmed number of samples at desired times.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 26, 2016
    Assignee: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Edward J. Seng, Marc Reuben Hutner
  • Publication number: 20160006441
    Abstract: An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Jeffrey Wade Sanders, Thomas Aquinas Repucci, Ronald A. Sartschev
  • Patent number: 9147620
    Abstract: Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one-shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 29, 2015
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Ronald A. Sartschev, Gregory A. Kannall
  • Publication number: 20150137838
    Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: Teradyne, Inc.
    Inventors: Howard Lin, Corbin L. Champion, Jan Paul Anthonie van der Wagt, Ronald A. Sartschev
  • Publication number: 20150128003
    Abstract: A test technique that may be implemented in an automated test system for testing semiconductor devices. The test technique may enable the fast detection of a signal transition, such as an edge, within a waveform and the timing of that event. Circuitry within a digital instrument that can be quickly and flexibly programmed may, at least in part, implement the test technique. That circuitry may be simply programmed with testing parameters, such that application of the technique may lead to faster test development and faster times. In operation, that circuitry receives parameters specifying parameters of a window over a waveform in which samples of the waveform will be taken to detect the signal transition. The circuitry may convert these parameters into control signals for other components in the test system, such as an edge generator or pin electronics, to take a programmed number of samples at desired times.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Edward J. Seng, Marc Reuben Hutner
  • Publication number: 20130260485
    Abstract: Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one-shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system.
    Type: Application
    Filed: April 18, 2012
    Publication date: October 3, 2013
    Applicant: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Ronald A. Sartschev, Gregory A. Kannall
  • Patent number: 8289039
    Abstract: In one embodiment, a channel board-to-DIB junction multi-module is provided which includes performance critical channel electronics modules within an enclosure encasing the plurality of performance critical channel electronics modules. A coolant distribution apparatus is provided within the enclosure to provide cooling within the enclosure. A channel board connection apparatus is located at a channel board end of the channel board-to-DIB junction multi-module and a cable-less connection apparatus is located at a DIB end of the channel board-to-DIB junction multi-module.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: October 16, 2012
    Assignee: Teradyne, Inc.
    Inventors: Keith Breinlinger, Edward Ostertag, Ronald A. Sartschev, Nicholas J. Teneketges
  • Patent number: 7991046
    Abstract: Calibrating jitter in a communication channel between test equipment and a connection for a device under test (DUT) includes sampling test data in the communication channel at about a point of the connection to produce sampled data, where the test data travels through the communication channel at a first rate, and where the test data is sampled at a second rate that is less than the first rate, determining a first amount of jitter in the sampled data relative to the test data, and determining a second amount of jitter at about the point of connection based on the first amount of jitter.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: August 2, 2011
    Assignee: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Ernest P. Walker, Li Huang
  • Patent number: 7856578
    Abstract: A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: December 21, 2010
    Assignee: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Ernest P. Walker
  • Publication number: 20100231250
    Abstract: In one embodiment, a channel board-to-DIB junction multi-module is provided which includes performance critical channel electronics modules within an enclosure encasing the plurality of performance critical channel electronics modules. A coolant distribution apparatus is provided within the enclosure to provide cooling within the enclosure. A channel board connection apparatus is located at a channel board end of the channel board-to-DIB junction multi-module and a cable-less connection apparatus is located at a DIB end of the channel board-to-DIB junction multi-module.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 16, 2010
    Inventors: Keith Breinlinger, Edward Ostertag, Ronald A. Sartschev, Nicholas J. Teneketges
  • Patent number: 7573957
    Abstract: A method and apparatus is provided to recover clock information embedded in a digital signal such as a data signal. A set of strobe pulses can be generated by routing an edge generator to a delay elements with incrementally increasing delay values. A set of latches triggered by incrementally delayed signals from the edge generator can capture samples of the data signal. An encoder can convert the samples to a word representing edge time and polarity of the sampled signal. The word representing edge time can be stored in memory. An accumulator can collect the average edge time over N samples. The average edge time can be adjusted with a fixed de-skew value to form the extracted clock information. The extracted clock information can be used as a pointer to the words stored in memory.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: August 11, 2009
    Assignee: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Ernest P. Walker
  • Patent number: 7574632
    Abstract: A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: August 11, 2009
    Assignee: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Ernest P. Walker
  • Patent number: 7560947
    Abstract: Circuitry for driving a pin of a device includes a first circuit path terminating in a first impedance, a second circuit path terminating in a second impedance, where the second impedance is less than the first impedance, and a selection circuit to control operation of the second circuit path. When the second circuit path is not configured for operation, the first circuit path is configured to output one of plural first voltage signals. When the second circuit path is in configured for operation, the second circuit path is configured to output a second voltage signal. The second voltage signal is greater than the plural first voltage signals.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: July 14, 2009
    Assignee: Teradyne, Inc.
    Inventor: Ronald A. Sartschev
  • Patent number: 7508228
    Abstract: A semiconductor device tester includes a parametric measurement unit (PMU) driver circuit that provides a DC test signal for testing a semiconductor device, and a feedback circuit that senses the DC test signal at an output of the PMU driver circuit and sends the sensed DC test signal to an input of the PMU driver circuit for compensating the DC test signal.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: March 24, 2009
    Assignee: Teradyne, Inc.
    Inventors: Ernest P. Walker, Ronald A. Sartschev
  • Publication number: 20080285636
    Abstract: Calibrating jitter in a communication channel between test equipment and a connection for a device under test (DUT) includes sampling test data in the communication channel at about a point of the connection to produce sampled data, where the test data travels through the communication channel at a first rate, and where the test data is sampled at a second rate that is less than the first rate, determining a first amount of jitter in the sampled data relative to the test data, and determining a second amount of jitter at about the point of connection based on the first amount of jitter.
    Type: Application
    Filed: May 18, 2007
    Publication date: November 20, 2008
    Applicant: TERADYNE, INC.
    Inventors: Ronald A. Sartschev, Ernest P. Walker, Li Huang
  • Patent number: 7323898
    Abstract: Circuitry for driving a pin includes a first resistive circuit connected to the pin, a first transistor circuit to connect the first resistive circuit to a logic level voltage in response to a trigger voltage, the first transistor circuit and the first resistive circuit together defining a termination impedance, and a driver circuit to apply the trigger voltage to the first transistor circuit. The driver circuit includes counterparts to the first resistive circuit and the first transistor circuit. The counterparts define a counterpart impedance that is controlled to control the trigger voltage and thereby control the termination impedance.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: January 29, 2008
    Assignee: Teradyne, Inc.
    Inventor: Ronald A. Sartschev