Abstract: Disclosed is a method for generating I/Q waveforms for transmission over a CDMA radio channel. The method includes steps of (a) summing, for each of a plurality N of channels, the state of I bits to form an Isum value having a sign bit, the state of Q bits to form a Qsum value having a sign bit, and a total number of active channels to form a channel sum value; (b) applying the Isum value and sign bit, the Qsum value and sign bit, and the channel sum value to an input of a multiplexer; and (c) time multiplexing the inputs to generate first and second sets of output bits. The first set of output bits includes a subset of the Isum value bits, a subset of the Qsum value bits, the I sign bit, and the channel sum value bits. The second set of output bits includes the subset of the Isum value bits, the subset of the Qsum value bits, the Q sign bit, and the channel sum value bits.

Abstract: A system for providing a high speed digital communication path between the processor of a host computer and the processors of one or more remote computers. The high speed digital communication path allows a remote computer to efficiently share the resources of the larger host computer such as high speed magnetic disk drives and printers. A host interface located at the host computer is connected to the internal host bus of the host computer. The host interface includes a host port and components which provide for the transfer of data from the host bus to the host port. The data bits presented at the host port are arranged in a parallel format. A communication cable conveys the parallel data bits from the host port to a remote port in a remote interface at a remote computer. The remote interface provides a random access memory and components for transferring data from the remote bus to the random access memory and vice-versa. Data bits presented at the remote port are also conveyed to the random access memory.

Abstract: A digital memory system wherein a plurality of frames in the memory, each frame holding a page of data, may be rapidly accessed utilizing static column dynamic random access memories (SCRAMs). The SCRAM devices are configured such that a page of data is located on corresponding rows of a plurality of SCRAM devices, the corresponding rows being referred to as frames. Once a row has been activated into static column mode, successive accesses to the same row may be made very rapidly. In the presently preferred embodiments, a plurality of banks are provided, each bank being capable of holding one page of data in static column mode. In the preferred embodiments, a tag register and comparator are provided which are associated with each bank. The tag register contains a portion of the address which previously caused an access to its corresponding bank. An address is presented to all the tag registers and comparators.