Patents by Inventor Ronald D. Fellman

Ronald D. Fellman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8891504
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Great Links G.B. Limited Liability Company
    Inventors: Ronald D. Fellman, Rene L. Cruz, Douglas A. Palmer, Bart Schade
  • Publication number: 20130073679
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.
    Type: Application
    Filed: October 5, 2012
    Publication date: March 21, 2013
    Applicant: Great Links G.B. Limited Liability Company
    Inventors: Ronald D. Fellman, Rene L. Cruz, Douglas A. Palmer, Bart Schade
  • Patent number: 8306053
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: November 6, 2012
    Assignee: Great Links G.B. Limited Liability Company
    Inventors: Ronald D. Fellman, Rene L. Cruz, Douglas A. Palmer, Bart Schade
  • Publication number: 20090196282
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.
    Type: Application
    Filed: May 27, 2008
    Publication date: August 6, 2009
    Applicant: Great Links G.B. Limited Liability Company
    Inventors: Ronald D. Fellman, Rene L. Cruz, Douglas A. Palmer, Bart Schade
  • Patent number: 7551647
    Abstract: Embodiments of the invention enable the synchronization of clocks across packet switched networks, such as the Internet, sufficient to drive a jitter buffer and other quality-of-service related buffering. Packet time stamps referenced to a local clock create a phase offset signal. A shortest-delay offset generator uses a moving-window filter to select the samples of the phase offset signal having the shortest network propagation delay within the window. This shortest network propagation delay filter minimizes the effect of network jitter under the assumption that queuing delays account for most of the network jitter. The addition of this filtered phase offset signal to a free-running local clock creates a time reference that is synchronized to the remote clock at the source thus allowing for the transport of audio, video, and other time-sensitive real-time signals with minimal latency.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: June 23, 2009
    Assignee: Qvidium Technologies, Inc.
    Inventors: Ronald D. Fellman, John C. Beer
  • Patent number: 7539187
    Abstract: A forward error correction (FEC) encoding system and method optimized for protecting real-time audio-video streams for transmission over packet-switched networks with minimal latency. Embodiments of this invention provide bandwidth-efficient and low-latency FEC for both variable and constant bit-rate MPEG-encoded audio and video streams. To maximize bandwidth-efficiency and playable frame rate for recovered media streams, embodiments of the invention may sort packets by content type and aggregate them into FEC blocks weighted by sensitivity in the recovered stream to packet loss of a particular content type. Embodiments of this invention may use temporal constraints to limit FEC block size and thereby facilitate their use in the transport of VBR streams.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: May 26, 2009
    Assignee: Qvidium Technologies, Inc.
    Inventors: Ronald D. Fellman, John C. Beer
  • Patent number: 7522528
    Abstract: An Automatic Repeat request (ARQ) error correction method optimized for protecting real-time audio-video streams for transmission over packet-switched networks. Embodiments of this invention provide bandwidth-efficient and low-latency ARQ for both variable and constant bit-rate audio and video streams. Embodiments of this invention use timing constraints to limit ARQ latency and thereby facilitate the use of ARQ packet recovery for the transport of both constant bit rate and variable bit rate media streams.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: April 21, 2009
    Assignee: QVidium Technologies, Inc.
    Inventors: Ronald D. Fellman, John C. Beer
  • Publication number: 20090070844
    Abstract: Enables video over IP distribution system and method that multicasts or broadcasts IP messages over a local layer 2 network (generally for example in a known local network, e.g., a network within an Internet service provider or video provider) to eliminate intermediate replication servers. The system thus utilizes a flat architecture that distributes the same number of video streams as pyramid architectures, but utilizes less hardware, e.g., less replication servers and less network switches. Systems may be configured to transmit multiple versions of the same broadcast, for example at different sizes, resolutions or aspect ratios or at different bit rates or any combination thereof. Groupings of the system allow for customized broadcast of the same video. With respect to quality of service, various clock synchronization, forward error correction (FEC), automatic repeat request (ARQ) methods and systems may be utilized to provide higher quality of service for any embodiment of the invention.
    Type: Application
    Filed: September 10, 2007
    Publication date: March 12, 2009
    Inventors: John C. BEER, Ronald D. Fellman
  • Publication number: 20040208158
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.
    Type: Application
    Filed: October 17, 2003
    Publication date: October 21, 2004
    Inventors: Ronald D. Fellman, Rene L. Cruz, Douglas A. Palmer, Bart Schade
  • Patent number: 6751231
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for time-sensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: June 15, 2004
    Assignee: Path 1 Network Technologies Inc.
    Inventors: Ronald D. Fellman, Rene L. Cruz
  • Patent number: 6661804
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for time-sensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: December 9, 2003
    Assignee: Path 1 Network Technologies, Inc.
    Inventors: Ronald D. Fellman, Rene L. Cruz, Douglas A. Palmer
  • Patent number: 6246702
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for time-sensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. One of the device adapters may be designated as a master timing device to synchronize each of the other device adapters.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: June 12, 2001
    Assignee: Path 1 Network Technologies, Inc.
    Inventors: Ronald D. Fellman, Rene L. Cruz, Douglas A. Palmer
  • Publication number: 20010002196
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for time-sensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter.
    Type: Application
    Filed: January 16, 2001
    Publication date: May 31, 2001
    Applicant: Path 1 Network Technologies, Inc., California Corporation
    Inventors: Ronald D. Fellman, Rene L. Cruz
  • Publication number: 20010002195
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for time-sensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.
    Type: Application
    Filed: January 17, 2001
    Publication date: May 31, 2001
    Applicant: Path 1 Network Technologies, Inc., California corporation
    Inventors: Ronald D. Fellman, Rene L. Cruz, Douglas A. Palmer
  • Patent number: 6215797
    Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for time-sensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: April 10, 2001
    Assignee: Path 1 Technologies, Inc.
    Inventors: Ronald D. Fellman, Rene L. Cruz
  • Patent number: 6141355
    Abstract: A network system for providing efficient transmission of real-time data and non-real-time data between a plurality of network devices, including an arbitration mechanism that provides a low cost and high performance mechanism for delivery of quality of service guarantees for time-sensitive data sharing a local area with non-time-sensitive data. Device adapters are placed at all access points to a local network. The device adapters limit admission rates and control the timing of all packets entering the network. An X-Hub placed at the center of the network provides for transparent, concurrent transport of signals transmitted by device adapters. Collisions may therefore be eliminated for time-sensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters and the X-Hub. The time reference defines a frame with a plurality of phases. Each of the phases defines a state of the X-Hub, and a state for each of the device adapters.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: October 31, 2000
    Assignee: Path 1 Network Technologies, Inc.
    Inventors: Douglas A. Palmer, Ronald D. Fellman, Rene L. Cruz
  • Patent number: 4401855
    Abstract: Improved apparatus for the linear predictive coding of human speech in which the speech is sampled through the use of analog filters and the linear predictive coding computations are performed with respect to such samples using digital techniques. The filters are MOS switched capacitor filters which can be implemented on a silicon chip together with the digital circuitry. Specific circuits for implementing two different linear predictive coding speech analysis techniques are disclosed.
    Type: Grant
    Filed: November 28, 1980
    Date of Patent: August 30, 1983
    Assignee: The Regents of the University of California
    Inventors: Robert W. Broderson, Paul J. Hurst, Ronald D. Fellman