Patents by Inventor Ronald L. Cline
Ronald L. Cline has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10559357Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.Type: GrantFiled: August 6, 2018Date of Patent: February 11, 2020Assignee: Lattice Semiconductor CorporationInventor: Ronald L. Cline
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Publication number: 20200043553Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.Type: ApplicationFiled: August 6, 2018Publication date: February 6, 2020Inventor: Ronald L. Cline
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Publication number: 20190279100Abstract: Various techniques are provided for providing neural networks with increased efficiency. In one example, a system includes a first artificial neural network (ANN), a second ANN, and a logic device. The first ANN is configured to receive a first plurality of data inputs associated with a data stream and process the first data inputs to generate a first inference output after a first latency. The second ANN is configured to receive a second plurality of data inputs associated with the data stream and process the second data inputs to generate a second inference output after a second latency less than the first latency. The logic device is configured to receive the second inference output before the first inference output is generated. Additional systems and methods are also provided.Type: ApplicationFiled: March 1, 2019Publication date: September 12, 2019Inventor: Ronald L. Cline
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Patent number: 10079054Abstract: Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.Type: GrantFiled: June 5, 2017Date of Patent: September 18, 2018Assignee: Lattice Semiconductor CorporationInventors: Senani Gunaratna, Brad Sharpe-Geisler, Ting Yew, Ronald L. Cline
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Patent number: 9672935Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.Type: GrantFiled: October 19, 2015Date of Patent: June 6, 2017Assignee: Lattice Semiconductor CorporationInventors: Ronald L Cline, Stewart Logie
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Publication number: 20160111168Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.Type: ApplicationFiled: October 19, 2015Publication date: April 21, 2016Inventors: Ronald L. Cline, Stewart Logie
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Patent number: 8694939Abstract: A method for determining a critical junction temperature for a user-design implemented in a field programmable gate array (programmable device), includes: obtaining a static power vs. temperature curve for the user-design implemented in the programmable device; obtaining a system thermal curve for the user-design implemented in the programmable device; and using the static power vs. temperature curve for the user-design implemented in the programmable device and the system thermal curve for the user-design implemented in the programmable device to determine the critical junction temperature.Type: GrantFiled: March 13, 2013Date of Patent: April 8, 2014Assignee: Xilinx, Inc.Inventors: Alan M. Frost, Matthew H. Klein, Ronald L. Cline
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Patent number: 8330517Abstract: A method and circuit for operating a bistable latch are provided. The state of input data is latched on a first edge of a clock signal. In response to every first edge of the clock signal, a control circuit causes power boost circuit to couple first and second complementary output nodes of the bistable latch to a power source. In response to detecting stable operation of the bistable circuit, the control circuit causes power boost circuit to decouple the first and second complementary output nodes from the power source.Type: GrantFiled: December 21, 2010Date of Patent: December 11, 2012Assignee: Xilinx, Inc.Inventor: Ronald L. Cline
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Patent number: 8159263Abstract: A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a plurality of level shifters couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port. The first signaling protocol is referenced to the voltage magnitude of the first voltage domain, and the second signaling protocol is referenced to the voltage magnitude of the second voltage domain. Means are disclosed for controlling the voltage magnitude of the respective power network of one or more of the voltage domains.Type: GrantFiled: April 29, 2010Date of Patent: April 17, 2012Assignee: Xilinx, Inc.Inventors: Tim Tuan, Ronald L. Cline, Arifur Rahman
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Patent number: 7893712Abstract: An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.Type: GrantFiled: September 10, 2009Date of Patent: February 22, 2011Assignee: Xilinx, Inc.Inventors: Chin Hua Tan, Shankar Lakka, Ronald L. Cline, James B. Anderson, Wayne E. Wennekamp
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Patent number: 7479805Abstract: A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.Type: GrantFiled: August 1, 2007Date of Patent: January 20, 2009Assignee: Xilinx, Inc.Inventors: Shi-dong Zhou, Gubo Huang, Andy T. Nguyen, Ronald L. Cline
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Patent number: 7265586Abstract: A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.Type: GrantFiled: February 25, 2005Date of Patent: September 4, 2007Assignee: Xilinx, Inc.Inventors: Shi-dong Zhou, Gubo Huang, Andy T. Nguyen, Ronald L. Cline
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Patent number: 6985019Abstract: A selectively enabled clamp circuit for limiting voltage overshoot on an input/output (I/O) pin of an associated integrated circuit (IC) device includes a single discharge transistor and a select circuit. The single discharge transistor is connected between the I/O pin and ground potential, and the select circuit is coupled to the I/O pin and includes an input to receive an enable signal and an output coupled to a gate of the signal discharge transistor. For some embodiments, the select circuit includes a level shifter circuit and a voltage detection circuit.Type: GrantFiled: April 13, 2004Date of Patent: January 10, 2006Assignee: Xilinx, Inc.Inventors: Shi-dong Zhou, Ping Zhang, Ronald L. Cline
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Patent number: 6842043Abstract: Level shifter circuits that provide fast operation when changing state while generating little crowbar current. Various embodiments are presented that include some of the following features added to conventional level shifters: additional pull-down transistors coupled to each output node and gated by the associated input signal; additional pull-up transistors coupled to each output node or cross-coupled internal node and gated by the associated input signal; additional pull-up transistors coupled to the cross-coupled internal nodes and gated by the opposing output node; and additional pull-down transistors on the output nodes gated by a low voltage power high. Some of these additional transistors allow the input signal to operate more quickly on the output nodes, causing more rapid transitions on the output signals and reducing crowbar current. The pull-downs gated by the low voltage power high ensure that little or no crowbar current occurs during the power-up sequence.Type: GrantFiled: March 11, 2003Date of Patent: January 11, 2005Assignee: Xilinx, Inc.Inventors: Andy T. Nguyen, Shi-dong Zhou, Ronald L. Cline
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Patent number: 6525561Abstract: A very fine-grained gate array cell is provided that includes a two-input logic device and a cascade NAND gate with buffered output. The NAND gate accepts a cascade input from another cell, and the cascade output of the NAND gate is provided as a cascade input to the other cell to facilitate the efficient implementation of cross-coupled devices. Each cell contains integral routing paths that facilitate a “sea of cells” layout approach. To ease the routing task, the output of each gate array cell is pre-wired so as to facilitate a programmed interconnection to each logic input of adjacent cells, near-adjacent cells, and far cells, and the aforementioned cascade interconnection with adjacent upper and lower cells. This configuration allows adjacent and near-adjacent cells to be easily interconnected to form macro cells that conform to higher level functional blocks.Type: GrantFiled: April 9, 2001Date of Patent: February 25, 2003Assignee: Koninklijke Philips Electronics N.V.Inventor: Ronald L. Cline
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Patent number: 6424567Abstract: A programmable cell comprises an externally loadable electrically erasable (EE) transistor cell that is configured to be independent of the currently active state of the programmed cell. When all of the EE cells are loaded with a new configuration, the contents of all of the EE cells are loaded into the corresponding programmable cells, preferably within one clock cycle. Because the entirety of the programmable cells can be pre-loaded with the new configuration, the time to effect a reconfiguration is one clock cycle. Because an EE cell is significantly smaller than a conventional four to six transistor storage cell, the area required to implement this single-clock-cycle reconfiguration capability is substantially less than traditional dynamically reprogrammable memory configurations. In an alternative embodiment, multiple EE cells can be associated with each programmable cell, thereby allowing a multiple-configuration capability.Type: GrantFiled: July 7, 1999Date of Patent: July 23, 2002Assignee: Philips Electronics North America CorporationInventors: Ronald L. Cline, Bernardo De Oliveira Kastrup Pereira
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Publication number: 20020011868Abstract: A very fine-grained gate array cell is provided that includes a two-input logic device and a cascade NAND gate with buffered output. The NAND gate accepts a cascade input from another cell, and the cascade output of the NAND gate is provided as a cascade input to the other cell to facilitate the efficient implementation of cross-coupled devices. Each cell contains integral routing paths that facilitate a “sea of cells” layout approach. To ease the routing task, the output of each gate array cell is pre-wired so as to facilitate a programmed interconnection to each logic input of adjacent cells, near-adjacent cells, and far cells, and the aforementioned cascade interconnection with adjacent upper and lower cells. This configuration allows adjacent and near-adjacent cells to be easily interconnected to form macro cells that conform to higher level functional blocks.Type: ApplicationFiled: April 9, 2001Publication date: January 31, 2002Applicant: Philips Electronics North AmericaInventor: Ronald L. Cline
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Patent number: 6294926Abstract: A very fine-grained gate array cell is provided that includes a two-input logic device and a cascade NAND gate with buffered output. The NAND gate accepts a cascade input from another cell, and the cascade output of the NAND gate is provided as a cascade input to the other cell to facilitate the efficient implementation of cross-coupled devices. Each cell contains integral routing paths that facilitate a “sea of cells” layout approach. To ease the routing task, the output of each gate array cell is pre-wired so as to facilitate a programmed interconnection to each logic input of adjacent cells, near-adjacent cells, and far cells, and the aforementioned cascade interconnection with adjacent upper and lower cells. This configuration allows adjacent and near-adjacent cells to be easily interconnected to form macro cells that conform to higher level functional blocks.Type: GrantFiled: July 16, 1999Date of Patent: September 25, 2001Assignee: Philips Electronics North America CorporationInventor: Ronald L. Cline
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Patent number: RE48570Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.Type: GrantFiled: February 4, 2019Date of Patent: May 25, 2021Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Ronald L. Cline, Stewart G. Logie
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Patent number: RE48625Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.Type: GrantFiled: May 9, 2018Date of Patent: July 6, 2021Assignee: Lattice Semiconductor CorporationInventors: Ronald L Cline, Stewart G. Logie