Patents by Inventor Ronald M. Smith

Ronald M. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10716568
    Abstract: A surgical stapling assembly comprising a staple cartridge carrier, an anvil, an outer surface, a closure member, a staple cartridge, and a firing system is disclosed. The anvil is rotatable between a first position and a second position. The closure member is slideable along the outer surface to hold the anvil in the second position. The closure member comprises a clearance opening. The staple cartridge is positioned within the staple cartridge carrier. The staple cartridge comprises staples removably stored therein. The staple cartridge and the anvil define a tissue gap therebetween when the anvil is in the second position. The clearance opening is aligned with the tissue gap when the anvil is in the second position. The firing system is configured to eject the staples from the staple cartridge during a staple firing stroke. The firing system engages the staple cartridge carrier and the anvil during the staple firing stroke.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: July 21, 2020
    Assignee: Ethicon LLC
    Inventors: Steven G. Hall, Randall J. Tanguay, Jeffrey D. Messerly, Galen C. Robertson, Andrew M. Zwolinski, Frederick E. Shelton, IV, Geoffrey C. Hueil, Mark S. Ortiz, Douglas B. Hoffman, Patrick A. Weizman, Dean B. Bruewer, Gregory B. Blair, Charles J. Scheib, Kevin R. Doll, Bret W. Smith, William D. Kelly, Ronald J. Kolata, Joshua R. Uth, William B. Weisenburgh, II, Jerome R. Morgan, Kyle P. Moore, Mark H. Ransick, Jeffrey S. Swayze, Thomas W. Huitema, Glen A. Armstrong, Shailendra K. Parihar, Donna L. Korvick, Richard W. Timm
  • Patent number: 10698073
    Abstract: Collocated access point (AP) harvest data is combined with accurate location-tagged harvest data to improve access point location estimates and to estimate the location of access points that could not be previously estimated.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: June 30, 2020
    Assignee: Apple Inc.
    Inventors: Brian Stephen Smith, Robert Mayor, Ronald K. Huang, Lukas M. Marti
  • Patent number: 10617650
    Abstract: The present invention provides a process for preparing enterically-coated lyospheres comprising a therapeutic agent comprising: a.) providing lyospheres comprising the therapeutic agent; b.) coating said lyospheres with an enteric polymer coating composition; and c.) isolating said enterically-coated lyospheres. In other embodiments, the invention provides dosage forms comprising a lyosphere comprising an effective amount of a therapeutic agent and an enteric polymer coating. In some embodiments, the therapeutic agent in the process or dosage form is a polypeptide, a protein, a peptide, a lipopeptide, a glycoprotein, a fusion protein, a protein conjugate, a cytokine, an enzyme, an antibody, an oligonucleotide, a vaccine vector, small molecule, a live virus, an inactivated virus, a virus-like particle, a viral protein subunit, an adjuvant, microbiome, a prebiotic, a probiotic, or an ectobiotic.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: April 14, 2020
    Assignee: Merck Sharp & Dohme Corp.
    Inventors: Akhilesh Bhambhani, Robert K. Evans, Pranav Gupta, Ronald L. Smith, Donna M. Williams
  • Patent number: 10613771
    Abstract: Provided are a computer program product, system, and method for processing a write of records to maintain atomicity for writing a defined group of records to multiple tracks. A write is received comprising defined groups of records to write to a plurality of tracks in the primary storage system. Sub-writes are generated to write the records in the defined groups in the write. At least one of the sub-writes includes records to write for at least one of the defined groups that spans multiple tracks in response to determining that at least one of the defined groups includes records that will be written to multiple tracks. The sub-writes are transmitted to the primary storage system to mirror to the secondary storage system to cause the secondary storage system to return complete in response to completing writing to all the tracks written to by the sub-write.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ronald E. Bretschneider, John R. Paveza, Beth A. Peterson, Max D. Smith, Gail A. Spear, Harry M. Yudenfriend
  • Patent number: 10606719
    Abstract: Provided are a computer program product, system, and method for mirroring writes of records to maintain atomicity for writing a defined group of records to multiple tracks. Sub-writes are received from a host system to write records in defined groups in a write, wherein at least one of the sub-writes includes records to write for at least one of the defined groups that spans multiple tracks. For each of the sub-writes including records for at least one of the defined groups that spans multiple tracks, the tracks in the sub-write with to the secondary storage system to cause the secondary storage system to apply the tracks upon receiving all the tracks for the sub-write. Complete is returned for the sub-write to the host system upon receiving confirmation from the secondary storage system that all the tracks for the sub-write have been applied to the secondary storage system.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald E. Bretschneider, John R. Paveza, Beth A. Peterson, Max D. Smith, Gail A. Spear, Harry M. Yudenfriend
  • Publication number: 20190377550
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Application
    Filed: August 25, 2019
    Publication date: December 12, 2019
    Inventors: Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, SR., Phil C. Yeh
  • Patent number: 10423388
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Sr., Phil C. Yeh
  • Publication number: 20190272149
    Abstract: Execution of a machine instruction in a central processing unit. A perform floating-point operation instruction and a test bit are obtained. If the test bit has a first value, a specified floating-point operation function is performed, and a condition code is set to a value determined by the specified function. If the test bit has a second value, a check is made to determine if the specified function is valid and installed on the machine. If the specified function is valid and installed on the machine, the condition code is set to one code value, and if the specified function is either not valid or not installed on the machine, the condition code is set to a second code value.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: Michel H.T. HACK, Ronald M. SMITH, SR.
  • Patent number: 10387117
    Abstract: Execution of a machine instruction in a central processing unit. A perform floating-point operation instruction and a test bit are obtained. If the test bit has a first value, a specified floating-point operation function is performed, and a condition code is set to a value determined by the specified function. If the test bit has a second value, a check is made to determine if the specified function is valid and installed on the machine. If the specified function is valid and installed on the machine, the condition code is set to one code value, and if the specified function is either not valid or not installed on the machine, the condition code is set to a second code value.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michel H. T. Hack, Ronald M. Smith, Sr.
  • Publication number: 20190220275
    Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Eric M. SCHWARZ, Ronald M. SMITH, SR.
  • Publication number: 20190211161
    Abstract: Vulcanizable elastomeric formulation are disclosed. The formulations comprise at least one elastomer; a vulcanizing agent comprising cyclododecasulfur; and a prevulcanization inhibitor, present in an amount, for example, from about 0.01 phr to about 10 phr.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Applicant: Eastman Chemical Company
    Inventors: Scott Donald Barnicki, Frederick Ignatz-Hoover, Robert Thomas Hembre, Andrew Neil Smith, Henk Kreulen, Aruna M. Velamakanni, Chenchy Lin, Ronald H. Arthur
  • Patent number: 10324719
    Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F. Cowlishaw, Shawn D. Lundvall, Ronald M. Smith, Sr., Phil C. Yeh
  • Patent number: 10286765
    Abstract: A tonneau cover system includes a cover assembly coupled to first and second side rails. The cover assembly includes a cover disposed over and coupled to a frame, a latch mechanism coupled to the frame and having a catch biased toward a latch position to secure the cover to the first side rail and retractable to an unlatch position to release the cover from the first side rail, a release device coupled to the frame and latch mechanism and actuatable to move the catch to the unlatch position, and an adjustment mechanism coupled to the latch mechanism. The adjustment mechanism has a first portion coupled to the catch and a second portion interacting with the first portion to adjust a vertical position of the catch relative to the frame transverse to a width-wise axis defined between the side rails, with the first and/or second portions forming a sloped profile.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 14, 2019
    Assignee: Rugged Liner, Inc.
    Inventors: Scott Williamson, David Kosinski, Michael Yang, Xichang Yan, Jianfeng Tong, Chengping Wei, Ronald Brian Smith, Daniel David Burger, James Mays, Taylor M. Hixson
  • Patent number: 10261787
    Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric M. Schwarz, Ronald M. Smith, Sr.
  • Publication number: 20190079730
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 14, 2019
    Inventors: Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Sr., Phil C. Yeh
  • Publication number: 20180329684
    Abstract: Execution of a machine instruction in a central processing unit. A perform floating-point operation instruction and a test bit are obtained. If the test bit has a first value, a specified floating-point operation function is performed, and a condition code is set to a value determined by the specified function. If the test bit has a second value, a check is made to determine if the specified function is valid and installed on the machine. If the specified function is valid and installed on the machine, the condition code is set to one code value, and if the specified function is either not valid or not installed on the machine, the condition code is set to a second code value.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: Michel H.T. Hack, Ronald M. Smith, SR.
  • Patent number: 10127014
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael F Cowlishaw, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Patent number: 10065347
    Abstract: A lead frame for insert molding in a plastic body is provided with an opening defining an edge suitable for detection by pattern recognition systems. During the insert molding process, a pin is positioned in the opening so that the opening remains void of plastic following the injection molding process.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: September 4, 2018
    Assignee: Illinois Tool Works Inc.
    Inventor: Ronald M. Smith
  • Publication number: 20180246721
    Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
    Type: Application
    Filed: April 19, 2018
    Publication date: August 30, 2018
    Applicant: International Business Machines Corporation
    Inventors: Eric M. SCHWARZ, Ronald M. Smith, SR.
  • Patent number: 10061560
    Abstract: A method and system are disclosed for executing a machine instruction in a central processing unit. The method comprises the steps of obtaining a perform floating-point operation instruction; obtaining a test bit; and determining a value of the test bit. If the test bit has a first value, (a) a specified floating-point operation function is performed, and (b) a condition code is set to a value determined by said specified function. If the test bit has a second value, (c) a check is made to determine if said specified function is valid and installed on the machine, (d) if said specified function is valid and installed on the machine, the condition code is set to one code value, and (e) if said specified function is either not valid or not installed on the machine, the condition code is set to a second code value.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michel H. T. Hack, Ronald M. Smith, Sr.