Patents by Inventor Ronald M. Smith

Ronald M. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160202952
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh
  • Patent number: 9378016
    Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Eric M. Schwarz, Ronald M. Smith, Sr.
  • Patent number: 9323497
    Abstract: A perform floating-point operation instruction is executed specifying a Test (T) bit of general register 0, if the T bit is ‘1’ the execution sets a condition code value indicating whether a specified conversion function is installed, if the T bit is ‘0’ the execution stores a result of a specified floating-point conversion function in general register 0 and sets a condition code value.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michel H. T. Hack, Ronald M. Smith, Sr.
  • Patent number: 9292256
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Publication number: 20160070538
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Application
    Filed: November 17, 2015
    Publication date: March 10, 2016
    Inventors: Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh
  • Publication number: 20150377193
    Abstract: A sensor assembly is configured to be securely connected to a portion of an engine, for example, of a vehicle. The sensor assembly may include a main body, a connector shroud extending from the main body, a port extending from the main body, a deflectable locking member extending from the main body, and a radial tab extending from the main body. The connector shroud is configured to receive an electrical connector that electrically connects the sensor assembly to an engine control unit. The port is configured to be inserted into an opening formed in the portion of the engine. The deflectable locking member and the radial tab cooperate to securely connect the sensor assembly to the portion of the engine, such as through rotation of the sensor assembly in relation to the engine.
    Type: Application
    Filed: February 8, 2014
    Publication date: December 31, 2015
    Inventor: Ronald M. SMITH
  • Patent number: 9201846
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: December 1, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F Cowlishaw, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Patent number: 9164699
    Abstract: A protocol for communicating with the timing facility used in a data processing network to provide synchronization is provided via the execution of a machine instruction that accepts a plurality of commands. The interaction is provided through the use of message request blocks and their associated message response blocks. In this way timing parameters may be determined, modified and communicated. This makes it much easier for multiple servers or nodes in a data processing network to exist as a coordinated timing network and to thus more cooperatively operate on the larger yet identical data files.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: October 20, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Scott M. Carlson, Donald Crabtree, Dennis J. Dahlen, Beth A. Glendening, Michel H. T. Hack, Denise M. Sevigny, Ronald M. Smith, Sr., David E. Whitney
  • Publication number: 20150251344
    Abstract: A lead frame for insert molding in a plastic body is provided with an opening defining an edge suitable for detection by pattern recognition systems. During the insert molding process, a pin is positioned in the opening so that the opening remains void of plastic following the injection molding process.
    Type: Application
    Filed: May 18, 2015
    Publication date: September 10, 2015
    Inventor: Ronald M. Smith
  • Patent number: 8972606
    Abstract: A protocol for communicating with the timing facility used in a data processing network to provide synchronization is provided via the execution of a machine instruction that accepts a plurality of commands. The interaction is provided through the use of message request blocks and their associated message response blocks. In this way timing parameters may be determined, modified and communicated. This makes it much easier for multiple servers or nodes in a data processing network to exist as a coordinated timing network and to thus more cooperatively operate on the larger yet identical data files.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Scott M. Carlson, Donald Crabtree, Dennis J. Dahlen, Beth A. Glendening, Michel H. T. Hack, Denise M. Sevigny, Ronald M. Smith, Sr., David E. Whitney
  • Publication number: 20150006859
    Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventors: Eric M. SCHWARZ, Ronald M. SMITH, SR.
  • Patent number: 8920906
    Abstract: A removable molding tab facilitates loading component parts into a mold by providing a body with holding configurations suitable to releasably secure the component parts in mold ready positions. The component parts are loaded into a mold as a preassembly with the removable tab. The tab is removed after the component parts are placed into the mold.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: December 30, 2014
    Assignee: Illinois Tool Works Inc.
    Inventor: Ronald M. Smith
  • Publication number: 20140325014
    Abstract: A protocol for communicating with the timing facility used in a data processing network to provide synchronization is provided via the execution of a machine instruction that accepts a plurality of commands. The interaction is provided through the use of message request blocks and their associated message response blocks. In this way timing parameters may be determined, modified and communicated. This makes it much easier for multiple servers or nodes in a data processing network to exist as a coordinated timing network and to thus more cooperatively operate on the larger yet identical data files.
    Type: Application
    Filed: June 13, 2014
    Publication date: October 30, 2014
    Inventors: Scott M. Carlson, Donald Crabtree, Dennis J. Dahlen, Beth A. Glendening, Michel H.T. Hack, Denise M. Sevigny, Ronald M. Smith, SR., David E. Whitney
  • Publication number: 20140304314
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.
    Type: Application
    Filed: June 20, 2014
    Publication date: October 9, 2014
    Inventors: Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, SR., Phil C Yeh
  • Patent number: 8838942
    Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eric M. Schwarz, Ronald M. Smith, Sr.
  • Publication number: 20140188962
    Abstract: A perform floating-point operation instruction is executed specifying a Test (T) bit of general register 0, if the T bit is ‘1’ the execution sets a condition code value indicating whether a specified conversion function is installed, if the T bit is ‘0’ the execution stores a result of a specified floating-point conversion function in general register 0 and sets a condition code value.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 3, 2014
    Applicant: International Business Machines Corporation
    Inventors: Michel H.T. Hack, Ronald M. Smith, SR.
  • Publication number: 20140181481
    Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
    Type: Application
    Filed: February 28, 2014
    Publication date: June 26, 2014
    Applicant: International Business Machines Corporation
    Inventors: Michael F. Cowlishaw, Shawn D. Lundvall, Ronald M. Smith, Phil C. Yeh
  • Patent number: 8762438
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Sr., Phil C. Yeh
  • Patent number: 8738792
    Abstract: Server time protocol (STP) messages and methods of exchange thereof are provided for facilitating synchronization of processing units of a timing network. The STP messages include exchange time parameters (XTP) commands and responses, and STP control (STC) commands and responses. XTP message exchange processing includes: generating an XTP message command at a first processing unit including a command transmit timestamp field set by the first processing unit and a command receive timestamp field which is unset by the first processing unit; transmitting the XTP message command to a second processing unit; setting the command receive timestamp field in the XTP command with the time the XTP command is received at the second processing unit; and generating an XTP message response at the second processing unit, the message response including the command transmit timestamp set by the first processing unit and the command receive timestamp set by the second processing unit.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Scott M. Carlson, Donald Crabtree, Dennis J. Dahlen, Noshir R. Dhondy, Michael H.T. Hack, Denise M. Sevigny, Ronald M. Smith, Sr., Judith A. Wierbowski
  • Publication number: 20140114641
    Abstract: A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.
    Type: Application
    Filed: December 31, 2013
    Publication date: April 24, 2014
    Applicant: International Business Machines Corporation
    Inventors: Shawn D. LUNDVALL, Ronald M. SMITH, SR., Phil Chi-Chung YEH