Patents by Inventor Ronald Raymond Palmer

Ronald Raymond Palmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testable programmable gate array and associated LSSD/deterministic test methodology
    Patent number: 6021513
    Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: February 1, 2000
    Assignee: International Business Machines Corporation
    Inventors: Wayne Kevin Beebe, Sally Botala, Scott Whitney Gould, Frank Ray Keyser, III, Wendell Ray Larsen, Ronald Raymond Palmer, Brian Worth
  • Testable programmable gate array and associated LSSD/deterministic test methodology
    Patent number: 5867507
    Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.
    Type: Grant
    Filed: December 12, 1995
    Date of Patent: February 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: Wayne Kevin Beebe, Sally Botala, Scott Whitney Gould, Frank Ray Keyser III, Wendell Ray Larsen, Ronald Raymond Palmer, Brian Worth
  • Programmable array I/O-routing resource
    Patent number: 5671432
    Abstract: A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: September 23, 1997
    Assignees: International Business Machines Corporation, Cadence Design Systems, Inc.
    Inventors: Allan Robert Bertolet, Kenneth Ferguson, Scott Whitney Gould, Eric Ernest Millham, Ronald Raymond Palmer, Brian Worth, Terrance John Zittritsch