Abstract: Disclosed is a storage controller for interfacing between a plurality of host systems and direct access storage devices (DASDs). The storage controller includes a bridge, a first host adaptor, and a first device adaptor that are configured to communicate with a first processor. A first DASD is linked to the first device adaptor. The bridge interfaces the first processor, the first host adaptor, and the first device adaptor. The storage controller further includes a second host adaptor and a second device adaptor that are configured to communicate with a second processor. A second DASD is linked to the second device adaptor. The bridge further interfaces the second processor, the second host adaptor, and the second device adaptor. After configuration, an input/output (I/O) request from at least one of the host systems is directed to the first DASD via the first host adaptor, the first processor, and the first device adaptor.

Abstract: A method and system for controlling data flow in a storage subsystem containing multiple cache and/or multiple NVS elements based on the operability of the cache arrays and NVS arrays. In a data processing system having a storage controller connecting a plurality of host processors and a plurality of storage devices, this invention provides a method and architecture for managing multiple storage elements within the controller, without a degradation in subsystem performance and without data integrity problems. A set of configuration registers is utilized by the microcontroller to direct cache and NVS access to the proper storage array. A configuration table is loaded with status information concerning the memory arrays at Initial Microcode Load(IML) and this information is periodically updated during controller operation.