Patents by Inventor Ronald S. Indeck

Ronald S. Indeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190123764
    Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
  • Patent number: 10229453
    Abstract: A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA).
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: March 12, 2019
    Assignee: IP RESERVOIR, LLC
    Inventors: David E. Taylor, Naveen Singla, Benjamin C. Brodie, Nathaniel Sutton McVicar, Justin Ryan Thiel, Ronald S. Indeck
  • Publication number: 20190073719
    Abstract: Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize financial market data in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.
    Type: Application
    Filed: November 5, 2018
    Publication date: March 7, 2019
    Inventors: Scott Parsons, David E. Taylor, Ronald S. Indeck
  • Patent number: 10191974
    Abstract: Disclosed herein are methods and systems for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of classification information about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device, a graphics processor unit (GPU), or chip multi-processor (CMP) to generate the classification metadata about the unstructured data.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 29, 2019
    Assignee: IP RESERVOIR, LLC
    Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, David E. Taylor
  • Patent number: 10158377
    Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: December 18, 2018
    Assignee: IP RESERVOIR, LLC
    Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
  • Patent number: 10121196
    Abstract: Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize financial market data in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 6, 2018
    Assignee: IP RESERVOIR, LLC
    Inventors: Scott Parsons, David E. Taylor, Ronald S. Indeck
  • Publication number: 20180276271
    Abstract: Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 27, 2018
    Inventors: Scott Parsons, David E. Taylor, Ronald S. Indeck
  • Publication number: 20180157504
    Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.
    Type: Application
    Filed: January 29, 2018
    Publication date: June 7, 2018
    Inventors: Roger D. Chamberlain, Mark Allen Franklin, Ronald S. Indeck, Ron K. Cytron, Sharath R. Cholleti
  • Patent number: 9990393
    Abstract: Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: June 5, 2018
    Assignee: IP Reservoir, LLC
    Inventors: Scott Parsons, David E. Taylor, Ronald S. Indeck
  • Patent number: 9898312
    Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 20, 2018
    Assignee: IP RESERVOIR, LLC
    Inventors: Roger D. Chamberlain, Mark Allen Franklin, Ronald S. Indeck, Ron K. Cytron, Sharath R. Cholleti
  • Publication number: 20170123866
    Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
  • Publication number: 20170102950
    Abstract: A multi-functional data processing pipeline is disclosed where the multi-functional pipeline comprises a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations. The multi-functional pipeline can be configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. In example embodiments, the pipelined data processing engines can include correlation logic, and such pipelines can be used to accelerate convolutional layers in machine-learning technology such as convolutional neural networks.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Inventors: Roger D. Chamberlain, Mark Allen Franklin, Ronald S. Indeck, Ron K. Cytron
  • Patent number: 9547824
    Abstract: Disclosed herein is a method and apparatus for hardware-accelerating various data quality checking operations. Incoming data streams can be processed with respect to a plurality of data quality check operations using offload engines (e.g., reconfigurable logic such as field programmable gate arrays (FPGAs)). Accelerated data quality checking can be highly advantageous for use in connection with Extract, Transfer, and Load (ETL) systems.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: January 17, 2017
    Assignee: IP Reservoir, LLC
    Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
  • Publication number: 20160328470
    Abstract: Disclosed herein are methods and systems for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of classification information about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device, a graphics processor unit (GPU), or chip multi-processor (CMP) to generate the classification metadata about the unstructured data.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 10, 2016
    Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, David E. Taylor
  • Patent number: 9396222
    Abstract: Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of metadata indexes about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device to generate the metadata about the unstructured data for the index.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: July 19, 2016
    Assignee: IP RESERVOIR, LLC
    Inventors: Ronald S. Indeck, David Mark Indeck
  • Patent number: 9363078
    Abstract: An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. An embodiment of the integrated circuit includes a run-time scalable block cipher circuit, wherein the run-time scalable block cipher circuit is run-time scalable to balance throughput with power consumption.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: June 7, 2016
    Assignee: IP Reservoir, LLC
    Inventors: David E. Taylor, Brandon Parks Thurmon, Ronald S. Indeck
  • Patent number: 9323794
    Abstract: Disclosed herein is a method and system for accelerating the generation of pattern indexes. In exemplary embodiments, regular expression pattern matching can be performed at high speeds on data to determine whether a pattern is present in the data. Pattern indexes can then be built based on the results of such regular expression pattern matching. Reconfigurable logic such a field programmable gate arrays (FPGAs) can be used to hardware accelerate these operations.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: April 26, 2016
    Assignee: IP Reservoir, LLC
    Inventors: Ronald S. Indeck, Naveen Singla, David E. Taylor
  • Publication number: 20160070583
    Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.
    Type: Application
    Filed: November 2, 2015
    Publication date: March 10, 2016
    Inventors: Roger D. Chamberlain, Mark Allen Franklin, Ronald S. Indeck, Ron K. Cytron, Sharath R. Cholleti
  • Patent number: 9176775
    Abstract: A re-configurable logic device such as a field programmable gate array (FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device is further configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 3, 2015
    Assignee: IP Reservoir, LLC
    Inventors: Roger D. Chamberlain, Mark Allen Franklin, Ronald S. Indeck, Ron K. Cytron, Sharath R. Cholleti
  • Patent number: 9020928
    Abstract: Methods and apparatuses for processing streaming data using programmable logic are disclosed. With an exemplary embodiment, a programmable logic device can be used to sort streaming data and provide a processor with access to the sorted data. With another exemplary embodiment, an Internet search engine can include a programmable logic device to perform match operations in response to search queries for web pages. With another exemplary embodiment, a programmable logic device is configured to perform match operations on streaming data while a processor is freed to perform other tasks.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 28, 2015
    Assignee: IP Reservoir, LLC
    Inventors: Ronald S. Indeck, Ron Kaplan Cytron, Mark Allen Franklin