Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: A modular computational structure includes a pipeline having first and second adder stages. Each adder stage includes a pair of adders which operate in parallel, and outputs ports of the first adder stage are coupled to input ports of the second adder stage. Rounding logic and an accumulator are included in the second stage. By varying the inputs to the first and second stages a variety of complex arithmetic functions suitable for video encoding can be implemented. Examples of the operations include completion of multiply and multiply-and-accumulate operations, averages of two values, averages of four values, and merged difference and absolute value calculation.

Abstract: Zero detect of a difference of binary operands is disclosed. If the difference is zero, the bit-complement of the difference is a string of one's, and therefore incrementing the string of one's generates a carry-out bit of one. Likewise, if the difference is non-zero, the bit-complement of the difference will contain one or more zero's, and therefore incrementing the bit-complemented difference will generate a carry-out bit of zero. The operands include a minuend and M subtrahends. One embodiment includes providing a result representing a bit-complement of the difference, and then inspecting a carry-out bit generated by incrementing the result.

Abstract: The average of two signed or unsigned integer numbers (A, B) rounded towards zero as prescribed in the MPEG standard is calculated in one instruction cycle by right shifting each of the operands by one bit position, summing the shifted operands, and incrementing the result as appropriate. The shifted operands are summed in an adder (302) that provides two versions of the average, one being the sum of the shifted operands and the other being the sum-plus-one of the shifted operands. A multiplexer (310) under control of a control circuit (308) selects one of the sum and sum-plus-one outputs. Incrementing (selecting the sum-plus-one output) is based on inspection of the shifted-out bits of the operands, the most significant bit of the sum, and a mode signal indicative of whether the operands are signed or unsigned values.

Abstract: The expression A-sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A-1) when A is less than zero, bit-complementing A when A is equal to zero, and bit-complementing (A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A-sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: A floating point subtraction is performed on a first and second floating point number to obtain an exponent result and a fraction result, the first floating point number has a first exponent and a first fraction and the second floating point number has a second exponent and a second fraction. A first adder determines an exponent difference between the first and second exponents and, concurrently with determining the exponent difference, a prediction circuit predicts a massive cancellation prediction and a second adder determines the difference between the first and second fraction and generates a massive cancellation fraction result. Then it is determined whether the massive cancellation result is valid and if so, the massive cancellation fraction result is selected as a basis for the fraction result. If not, a result from the no massive cancellation path is selected as the basis for the fraction result.

Abstract: A parallel multiplier for multiplying a multiplicand and multiplier with large bit lengths as well as simultaneously multiplying several multiplicands and multipliers with smaller bit lengths is disclosed. The parallel multiplier receives an N-bit multiplicand operand, an M-bit multiplier operand, and a data length signal. The parallel multiplier calculates an N+M bit product of an N-bit multiplicand from the multiplicand operand and an M-bit multiplier from the multiplier operand when the data length signal selects a first bit length. Furthermore, the parallel multiplier simultaneously calculates an (N+M)/2 bit first product of an N/2 bit first multiplicand from the multiplicand operand and an M/2 bit first multiplier from the multiplier operand, and an (N+M)/2 bit second product of an N/2 bit second multiplicand from the multiplicand operand and an M/2 bit second multiplier from the multiplier operand when the data length signal selects a second bit length.

Abstract: A method and apparatus for right-shifting a signed or unsigned integer operand and rounding a fractional intermediate result towards or away from zero to obtain an integer result as prescribed by the MPEG standard in a single instruction cycle is disclosed. The apparatus includes a right-shifter for right-shifting the operand to obtain a fractional intermediate result that includes integer bits and fractional bits. The apparatus also includes a control circuit for generating an increment signal in response to a sign bit of the operand, the fractional bits, a mode signal indicative of whether the operand is signed or unsigned, and a round signal indicative of whether round towards zero or round away from zero is selected.

Abstract: A fused floating point multiply-and-accumulate unit includes a multiplier which uses a modified Booth's algorithm to generate a sum and a carry representing a product of mantissas. An artifact of this algorithm is that the sum or carry may represent a negative value even though both mantissas are positive. The negative value may have a sign bit from sign extension or sign encoding of partial products in the multiplier. An artifact of the signed bit is a false carry out that results from canceling the sign bit. A 3-input adder simultaneously combines the sum and carry from the multiplier and performs the accumulation. The adder includes carry correction logic to suppress false carries and prevents a false carry from affecting more significant bits of the value being accumulated.

Abstract: An initial estimate of a reciprocal of a floating point number is generated in one addition having correct sign, exponent and up to five or more bits of precision in the fraction by subtracting the input floating point number from a constant. The constant is determined such that subtracting the floating point number from the constant results in bit complementing the most significant m bits (f.sub.0 . . . f.sub.m), 1.ltoreq.m.ltoreq.n, of the fractional part of the floating point number to provide 1.f.sub.0 . . . f.sub.m , negating the exponent E and subtracting 1, to provide an initial estimate of the exponent=-E-1, and including in the constant a correction factor to further improve the initial estimate.

Abstract: The n-bit average of four signed or unsigned n-bit integer operands (A, B, C and D) rounded towards zero as prescribed in the MPEG standard is calculated in one instruction cycle by appending two bits to a left side of each of the operands to provide four n+2 bit extended operands, summing the extended operands to provide an n+2 bit sum, removing the two least significant bits of the n+2 bit sum to provide an n-bit sum, and incrementing the n-bit sum as appropriate. An append circuit (302) appends two bits to the left sides of the operands, and the extended operands are coupled to an adder circuit (306) that includes adder logic (308) and an n-bit carry lookahead adder (310). The adder logic (308) provides the two least significant bits of the sum of the extended operands, along with n partial sum bits and n partial carry bits to the adder (310).

Abstract: The expression A-sign(A), where A is a signed binary integer represented in 2's complement form, sign (A) is equal to one when A is greater than zero, sign (A) is equal to zero when A is zero, and sign (A) is equal to negative one when A is less than zero, is calculated by bit-complementingA, bit-complementing (A-1) when A is less than zero, bit-complementing A when A is equal to zero, and bit-complementing (A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A-sign (A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: The expression 2A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A+A+2) when A is less than zero, bit-complementing (A+A+1) when A is equal to zero, and bit-complementing all bits except a least significant bit of (A+A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+A+1) and a second carry-out bit from (A+A+2) have different logical values. In this manner, 2A+sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: An initial estimate of a reciprocal of a square root of a floating point number is generated by subtracting the input floating point number from a constant and shifting the results to the right by one bit. Additionally, the initial estimate of a reciprocal of a square root of a floating point number can be determined by decrementing the exponent by one, shifting the exponent and fraction to the right by one bit, and subtracting the result from predetermined constant. The estimate for the reciprocal square root can also be determined by shifting the floating point number to the right by one bit and subtracting the shift result from a predetermined number to generate the initial estimate.

Abstract: A method and apparatus in accordance with the present invention provides for multiplying and/or dividing an operand by 2.sup.N using an arithmetic shifter where N is an integer represented in 2's complement form. The invention multiplies an operand by 2.sup.N by left-shifting the operand by N bit positions when N is positive and right-shifting the operand by the absolute value of N bit positions when N is negative, and divides an operand by 2.sup.N by right-shifting the operand by N bit positions when N is positive and left-shifting the operand by the absolute value of N bit positions when N is negative.

Abstract: The absolute difference of two signed or unsigned integer numbers (A, B) is calculated in one instruction cycle by bit-complementing the B operand, summing the A and bit-complemented B operands to obtain an intermediate result, detecting whether the intermediate result overflows, then either incrementing the intermediate result or bit-complementing the intermediate result as appropriate. The B operand is bit-complemented by a first inverter circuit (302). The A and bit-complemented B operands are summed in an adder (304) that provides a sum and sum-plus-one output. The sum output is bit-complemented by a second inverter circuit (306). A multiplexer (310) under the control of a control circuit (308) selects one of the bit-complemented sum output and sum-plus-one output, based on inspection of the most significant bits of the A operand, B operand, and sum output, a carry-out bit from the sum output, and a mode signal indicative of whether the operands are signed or unsigned values.

Abstract: A selected one of the expressions 2A+sign(A), 2A-sign(A), A+sign(A), and A-sign(A) is calculated, where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero. Advantageously, the selected sign 3 expression can be calculated by a general purpose computer in a single instruction cycle.

Abstract: The present invention supports vector-processor instructions that allow a programmer to specify the size and location of a particular vector element stored in a vector register. A mask generator circuit includes a mask-selector circuit, an index circuit, and a left shifter. The mask-selector circuit decodes a portion of the vector instruction indicating vector-element size and selects a mask appropriate for selecting an element of that size. The index circuit decodes both the vector-size information and that portion of the vector instruction indicating the location of the particular vector element to be masked. The index circuit uses this information to determine the number of places (the "shift count") that the mask must be shifted to correspond to the selected vector element. The shifter, upon receiving the mask and the shift count, shifts the mask by the shift count and provides the resulting output signal to the vector processor. This output signal is then used to select only the vector element specified.

Abstract: The expression A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementingA, bit-complementing(A+1) when A is less than zero, bit-complementing A when A is equal to zero, bit-complementing(A-1) when A is greater than zero and odd, and bit-complementingall bits except a least significant bit of A when A is greater than zero and even. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A+sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: The expression 2A-sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A+A) when A is less than zero, bit-complementing (A+A+1) when A is equal to zero, and bit-complementing (A+A+2) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+A+1) and a second carry-out bit from (A+A+2) have different logical values. In this manner, 2A-sign(A) can be calculated by a general purpose computer in a single instruction cycle.