Patents by Inventor Rongsheng Yang

Rongsheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9496304
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is coupled to selectively transfer the image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure disposed in the semiconductor material. The DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. The DTI structure includes a doped semiconductor material disposed inside the DTI structure that is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: November 15, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Dyson H. Tai
  • Publication number: 20150236058
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is coupled to selectively transfer the image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure disposed in the semiconductor material. The DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. The DTI structure includes a doped semiconductor material disposed inside the DTI structure that is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Dyson H. Tai
  • Patent number: 9054007
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 9, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Hsin-Chih Tai
  • Publication number: 20150048427
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: Omnivision Technologies, Inc.
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Hsin-Chih Tai
  • Patent number: 8946795
    Abstract: Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 3, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Sing-Chung Hu, Duli Mao, Hsin-Chih Tai, Yin Qian, Vincent Venezia, Rongsheng Yang, Howard E. Rhodes
  • Publication number: 20120319242
    Abstract: Forming a doped isolation region in a substrate during manufacture of an image sensor. A method of an aspect includes forming a hardmask layer over the substrate, and forming a photoresist layer over the hardmask layer. An opening is formed in the photoresist layer over an intended location of the doped isolation region. An opening is etched in the hardmask layer by exposing the hardmask layer to one or more etchants through the opening. The opening in the hardmask layer may have a width of less than 0.4 micrometers. The doped isolation region may be formed in the substrate beneath the opening in the hardmask layer by performing a dopant implantation that introduces dopant through the opening in the hardmask layer. The method of an aspect may include forming sidewall spacers on sidewalls of the opening in the hardmask layer and using the sidewall spacers as a dopant implantation mask.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Keh-Chiang Ku, Yin Qian, Gang Chen, Rongsheng Yang, Howard Rhodes
  • Patent number: 8330195
    Abstract: An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 11, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Vincent Venezia, Ashish Shah, Rongsheng Yang, Duli Mao, Yin Qian, Hsin-Chih Tai, Howard E. Rhodes
  • Publication number: 20120280109
    Abstract: Techniques for promoting conductivity in a substrate for a pixel array. In an embodiment, an isolation region and a dopant well are disposed within an epitaxial layer adjoining the substrate, where a portion of the dopant well is between the substrate and a portion of the isolation well. In another embodiment, a contact is further disposed within the epitaxial layer, where a portion of the isolation region surrounds a portion of the contact.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Keh-Chiang Ku, Rongsheng Yang
  • Patent number: 8273619
    Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Kurt D. Beigel, Fred D. Fishburn, Rongsheng Yang
  • Publication number: 20120235212
    Abstract: Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 20, 2012
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Gang Chen, Sing-Chung Hu, Duli Mao, Hsin-Chih Tai, Yin Qian, Vincent Venezia, Rongsheng Yang, Howard E. Rhodes
  • Patent number: 8253178
    Abstract: An example complementary metal oxide semiconductor (CMOS) image sensor includes an epitaxial layer, an array of pixels, and a trench capacitor. The array of pixels are formed on a front side of the epitaxial layer in an pixel array area of the image sensor. The array of pixels includes one or more shallow trench isolation structures disposed between adjacent pixels for isolating the pixels in the pixel array area. The trench capacitor is formed on the front side of the epitaxial layer in a peripheral circuitry area of the image sensor.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: August 28, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Rongsheng Yang, Zhiqiang Lin
  • Publication number: 20110085067
    Abstract: An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type.
    Type: Application
    Filed: December 14, 2010
    Publication date: April 14, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Vincent Venezia, Ashish Shah, Rongsheng Yang, Duli Mao, Yin Qian, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 7875918
    Abstract: An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: January 25, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventors: Vincent Venezia, Ashish Shah, Rongsheng Yang, Duli Mao, Yin Qian, Hsin-Chih Tai, Howard E. Rhodes
  • Publication number: 20100297822
    Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
    Type: Application
    Filed: August 2, 2010
    Publication date: November 25, 2010
    Inventors: Hongmei Wang, Kurt D. Beigel, Fred D. Fishburn, Rongsheng Yang
  • Publication number: 20100271524
    Abstract: An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Vincent Venezia, Ashish Shah, Rongsheng Yang, Duli Mao, Yin Qian, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 7767514
    Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Kurt D. Beigel, Fred D. Fishburn, Rongsheng Yang
  • Patent number: 7674670
    Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: March 9, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Kurt D. Beigel, Fred D. Fishburn, Rongsheng Yang
  • Patent number: 7638392
    Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: December 29, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Kurt D. Beigel, Fred D. Fishburn, Rongsheng Yang
  • Patent number: 7442600
    Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: October 28, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Kurt D. Beigel, Fred D. Fishburn, Rongsheng Yang
  • Patent number: 7259442
    Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: August 21, 2007
    Assignee: Micron Technology, Inc.
    Inventors: David Y. Kao, Rongsheng Yang