Roubik Gregorian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A charge pump circuit that is capable of generating a voltage that is greater in absolute magnitude than that of the substrate voltage Vsub in circuits where the substrate cannot be pumped to a voltage that is greater in absolute magnitude than Vsub is disclosed. Various innovative circuit techniques are used to implement a, for example, negative charge pump circuit in an N-well CMOS process with all PMOS transistors. The negative charge pump circuit according to the present invention can reliably drive on-chip transmission line termination switches.
Abstract: Power dissipation is reduced in a video DAC by providing a sleep mode in which DAC current sources are shut off during the blanking period in a manner that allows them to be rapidly turned back on at the end of sleep mode. In particular, a digital to analog converter includes a current source for producing a current, a current steering circuit connected to the current source, the current steering circuit including switches responsive to first and second control signals, respectively, for steering the current into either a load or a current return path, and a control circuit for generating the first and second signals each as a logical combination of a video data signal and a sleep signal. The sleep signal, when it is active, causes both the first and second switches to turn off, which in turn causes the current source to turn off. In a preferred embodiment, the switches are MOSFETS having low gate capacitance.
Abstract: A circuit technique to achieve 14-bit resolution in a charge-redistribution CMOS analog-to-digital converter. The sign bit plus the six most significant bits are obtained using a 6-bit capacitor array, the next five bits are determined using a resistor array, and finally the last two bits are obtained by use of a second 2-bit capacitor array. The area of the resulting 14-bit A/D converter is not appreciably larger than a corresponding 12-bit A/D converter. The 6-bit capacitor array is realized by connecting unit capacitors of a unit capacitor array. In the second capacitor array, at least one of the capacitors is realized by subdividing the unit capacitor. Since the accuracy of capacitors in the second capacitor array need not be as great as the accuracy of capacitors in the 6-bit capacitor array, subdividing the unit capacitor does not affect the accuracy of the converter.
Abstract: An apparatus for generating a substantially constant voltage control signal using either one of a voltage reference source and a current reference source includes a transistor device responsive to a supply voltage and the voltage control signal to produce a controlled current, an operational amplifier device for generating the voltage control signal in response to the voltage reference source, and a switching device for generating the voltage control signal in response to the current reference source. When the switching device is in one state thereof, an output signal of the operational amplifier device is connected through the transistor device in a closed loop back to an input terminal of the operational amplifier device. When the switching device is in another state thereof, the output signal of the operational amplifier device is connected directly in the closed loop back to an input terminal of the operational amplifier device.
Abstract: Echo attenuation facilitates achievement of efficient, full-duplex data communications on two-wire channels. Major advantages are achieved by using an adaptive hybrid in conjunction with echo cancellation. When needed, the adaptive hybrid reduces the amplitude range requirements on the echo canceller and on analog-to-digital conversion, thereby reducing overall cost. This reduction in range requirements reduces the digital word-size required for high-performance echo cancellation and reduces the bit-accuracy needed in the analog-to-digital converter. These reductions in needed word-size and bit accuracy substantially reduce implementation cost. Normally, the adaptive hybrid is used to reduce near-end echoes, which are usually much larger than far-end echoes. The echo canceller attenuates the remaining near-end echo and the far-end echo. Two major objectives are: (1) Cost effectiveness and (2) versatile, effective correction of echoes with various, realistic characteristics.
Abstract: An exponential analog-to-digital converter comprises two gain stages, each of which includes a binary-weighted capacitor array. The capacitors are switched in succession to multiply the gain of a sampled analog input signal, while a counter counts down for each switching step from an initial setting of binary 111. When the gain signal has a value outside a predetermined reference voltage range, a 3-bit binary digital word representative of the analog input signal sample is registered in the counter. If the gain signal produced after all the capacitors have been switched in to provide the maximum gain does not fall outside the reference range, then the binary word stored in the counter for the sample of the analog signal is 000.
Abstract: A voltage measurement circuit is provided which can be used in a single supply situation, which has a measurement range from rail to rail and which uses a reference voltage which can lie anywhere between the rails but not at the rail to which measurements are to be referenced. The unknown voltage is sampled to a first plate of a capacitor. The second plate of the capacitor is connected to ground. The first plate of the capacitor is then connected to the first input of a comparator, the second input being connected to receive the reference voltage. If the unknown voltage is less than the reference voltage, the second plate of the capacitor is disconnected from ground and then connected to receive the reference voltage. Otherwise it remains connected to ground. The first plate of the capacitor is then connected to a constant current source, causing the voltage at the first comparator input to decrease linearly with time.
Abstract: A novel switched capacitor gain stage uses a unique circuit design and clocking technique that reduces the component mismatch offset voltage and the clock-induced feedthrough offset voltage produced by the circuit. The total capacitance ratio between the input capacitors and the feedback capacitor necessary to achieve a desired total gain is also minimized.
Abstract: A unique CVSD CODEC is provided utilizing switched capacitor technology. This CVSD CODEC includes a syllabic filter which provides one of a large number of possible step sizes, thereby allowing the CVSD CODEC to accurately track and convert a wide range of input voltages. The CVSD CODEC includes coincidence logic, which determines how accurately the input voltage is being tracked, and a syllabic filter which provides an appropriate step size based upon the output signals of the coincidence logic. Large step sizes are provided for converting input voltages having large magnitudes, and small step sizes are used to convert input voltages having small magnitudes, thereby providing the very accurate resolution of input voltages over the wide range of magnitudes, while minimizing the bit rate required.
Abstract: In one embodiment of this invention, a uniquely designed switched capacitor multiplier/adder (129) is provided which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit significantly reduces the space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This invention provides a novel structure and method which minimizes error components in the synthesized speech signal due to voltage errors inherent in the use of analog sample and hold circuits which are used to store the forward and backward prediction errors utilized in the linear predictive coding technique. Using the method of this invention, the inherent error components are alternatively inverted and not inverted upon each clock cycle of the multiplier/adder.
Abstract: This invention provides a uniquely designed switched capacitor multiplier/adder (129) which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit results in a significant reduction in space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This reduction in size results in a significant reduction in the manufacturing costs for this circuit over prior art circuits, and additionally allows the option of including on the speech synthesis chip a memory for the storage of binary representations of to-be-synthesized speech patterns.
Abstract: An operational amplifier gain stage utilizing switched capacitor resistor equivalent circuits is designed utilizing a delayed clock reference signal (.phi..sub.D, .phi..sub.D) in a unique manner, thereby eliminating the effects of spurious error voltages (E.sub.S) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch. A single dummy switch (31) is utilized to further minimize the spurious voltage generated by this single MOSFET switch.
March 3, 1981
Date of Patent:
September 13, 1983
American Microsystems, Inc.
Gideon Amir, Yusuf Haque, Roubik Gregorian
Abstract: An integrator circuit utilizing an operational amplifier (19) and switched capacitor elements (11, 13 and 16) in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage (V.sub.OUT) free from the effects of voltage offsets inherent in operational amplifiers.
Abstract: An interpolation or smoothing filter circuit for a switched-capacitor system which transforms the sampled-and-held output signals from a switched-capacitor filter into sampled-and-held signals with a doubled sample rate. The circuit comprises an operational amplifier whose noninverting input lead is connected to a switched capacitor network which receives the sampled-and-held input signals at the normal sample rate. The network includes two separate capacitors controlled by switches operable at two alternating clock phases and connected to provide the desired summation and holding of charges. Feedback leads connected between the amplifier output lead and its noninverting input lead and containing additional capacitors cooperate with the input network to produce an output signal that is sampled-and-held at twice the sample rate of the input signal.
Abstract: A switched-capacitor cosine filter for a sampled-data system functions to reject extraneous frequency components of an incoming analog signal around the sampling frequency, thereby avoiding aliasing. The filter comprises an operational amplifier whose inverting input receives input signals through a switched input capacitor controlled by a four-switch network controlled by alternating clock phases and feedback signals from the amplifier output through a feedback capacitor. The transfer function of the circuit provides a zero of transmission at the sampling frequency, thereby eliminating unwanted frequency components. A self-contained version of the cosine filter is provided by the addition of another grounded switched capacitor with appropriately timed switches in the feedback network.
Abstract: An elliptic state variable filter uses switched capacitors controlled by an arrangement of switches that provides for a frequency response independent of stray capacitors in the circuit. The filter section comprises three integrating operational amplifiers connected in series, with a feedback connection between the output of the second operational amplifier and the circuit input to the first operational amplifier. Signals via a feed forward connection from the circuit input and the outputs of the first and second operational amplifier are summed by the third operational amplifier. Transmission zeros of the filter transfer function are realized independent of poles and with a feed forward arrangement which places them inherently on the unit circle and produces infinite loss at each zero frequency despite variations in capacitor ratios in the circuit.
Abstract: A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the multiplier for rounding its final product off to a predetermined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off.
Abstract: A high-pass switched capacitor biquadratic filter based on the bilinear z-transform. The filter comprises first and second integrating operational amplifiers connected in series and in combination with a third operational amplifier that serves as a sample and hold and also generates one simple pole and zero pair in the circuit transfer function thereby enabling the circuit to provide for a high degree of filter efficiency in a preselected frequency range. The operational amplifiers are connected to and operate in cooperation with capacitors of a predetermined size which are switched on and off continuously by two phase clock signals supplied to the circuit. The loss characteristic of the filter can be programmed by varying the clocking frequency. Higher order filters can be obtained by the tandem connection of second order circuit sections followed by one or more first order pole-zero section.
Abstract: A switched capacitor sampled data elliptic filter for data transmission or communication systems is disclosed. The filter section comprises three integrating operational amplifiers connected in series with a negative feedback connection between the output of the second operational amplifier and the input to the first operational amplifier, which is also connected to the input voltage source. Signals via a feed forward connection from the input voltage source and the outputs of the first and second operational amplifiers are summed by the third operational amplifier. Switched capacitors in the feed forward connection, the negative feedback connection, the inputs to all three operational amplifiers and in feedback sections of the first and third operational amplifiers are all connected to a two-phase clock driver operated at a preselected frequency.