Patents by Inventor Rudolf Mayrhuber

Rudolf Mayrhuber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10192739
    Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 29, 2019
    Assignee: SILTRONIC AG
    Inventors: Peter Storck, Guenter Sachs, Ute Rothammer, Sarad Bahadur Thapa, Helmut Schwenk, Peter Dreier, Frank Muemmler, Rudolf Mayrhuber
  • Publication number: 20140048848
    Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.
    Type: Application
    Filed: May 23, 2012
    Publication date: February 20, 2014
    Applicant: SILTRONIC AG
    Inventors: Peter Storck, Guenter Sachs, Ute Rothammer, Sarad Bahadur Thapa, Helmut Schwenk, Peter Dreier, Frank Muemmler, Rudolf Mayrhuber
  • Patent number: 5710077
    Abstract: A method for the generation of stacking-fault-induced damage on the back of emiconductor wafers is by treating the back with loose hard-material particles which are suspended in a liquid. The back of the semiconductor wafer is brought into contact with the suspended hard-material particles and the hard-material particles are propelled tangentially to the back, under which circumstances they exert on the back of the semiconductor wafer forces which have essentially only tangentially directed components.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: January 20, 1998
    Assignee: Wacker Siltronic Gesellschaft fur Halbleitermaterialien AG
    Inventors: Gerhard Brehm, Rudolf Mayrhuber, Johann Niedermeier
  • Patent number: 4900363
    Abstract: A process and liquid preparation is disclosed for removing residues from ers sawn from crystalline rods. In sawing rod-shaped workpieces such as semiconductor rods, for example, into wafers, by means of an internal-hole saw, auxiliary sawing materials such as for example cutting strips are often attached to the rods. According to the present invention, the residues of such auxiliary sawing materials remaining on the wafers obtained after the sawing operation can be removed particularly easily by means of immersion in baths of aqueous carboxylic solutions and, in particular, aqueous formic acid.
    Type: Grant
    Filed: March 25, 1988
    Date of Patent: February 13, 1990
    Assignee: Wacker-Chemitronic Gesellschaft fur Elektronik-Grundstoffe m.b.H.
    Inventors: Gerhard Brehm, Manuela Knipf, Rudolf Mayrhuber, Jurgen Schuhmacher, Max Stadler