Patents by Inventor Ruei-Wun SUN

Ruei-Wun SUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11012073
    Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
  • Publication number: 20200350916
    Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
  • Patent number: 10735001
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
  • Publication number: 20190319624
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 17, 2019
    Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
  • Patent number: 9323881
    Abstract: An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: April 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Ruei-Wun Sun, Hung-Jung Tseng, Shun Li Chen, Li-Chun Tien
  • Publication number: 20140332971
    Abstract: An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.
    Type: Application
    Filed: July 25, 2014
    Publication date: November 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Jen TSENG, Ting-Wei CHIANG, Wei-Yu CHEN, Ruei-Wun SUN, Hung-Jung TSENG, Shun Li CHEN, Li-Chun TIEN
  • Patent number: 8819610
    Abstract: An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Ruei-Wun Sun, Hung-Jung Tseng, Shun Li Chen, Li-Chun Tien
  • Publication number: 20140195997
    Abstract: An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks.
    Type: Application
    Filed: February 27, 2013
    Publication date: July 10, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Jen TSENG, Ting-Wei CHIANG, Wei-Yu CHEN, Ruei-Wun SUN, Hung-Jung TSENG, Shun Li CHEN, Li-Chun TIEN