Patents by Inventor Ruey-Hsin Liu

Ruey-Hsin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252545
    Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 15, 2019
    Inventors: YOGENDRA YADAV, CHI-CHIH CHEN, RUEY-HSIN LIU, CHIH-WEN YAO
  • Patent number: 10381259
    Abstract: A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alex Kalnitsky, Chih-Wen Yao, Jun Cai, Ruey-Hsin Liu, Hsiao-Chin Tuan
  • Publication number: 20190237485
    Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Publication number: 20190189793
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 12, 2019
    Publication date: June 20, 2019
    Inventors: CHIH-CHANG CHENG, FU-YU CHU, RUEY-HSIN LIU, KUANG-HSIN CHEN, CHIH-HSIN KO, SHIH-FEN HUANG
  • Patent number: 10304829
    Abstract: A device includes a vertical transistor and a lateral transistor on a substrate, wherein the vertical transistor comprises a first gate in a first trench, a second gate in a second trench, a source and a drain, wherein the source and the drain are on opposite sides of the first trench and the lateral transistor and the drain are on opposite sides of the second trench.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20190131414
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 2, 2019
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Patent number: 10276596
    Abstract: Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 10269954
    Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yogendra Yadav, Chi-Chih Chen, Ruey-Hsin Liu, Chih-Wen Yao
  • Publication number: 20190109229
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20190051745
    Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: October 15, 2018
    Publication date: February 14, 2019
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 10205024
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang
  • Patent number: 10170589
    Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu, Chun-Wai Ng
  • Patent number: 10164085
    Abstract: A method comprises forming a buried layer over a substrate, forming an epitaxial layer over the buried layer, forming a first trench and a second trench in the buried layer and the epitaxial layer, wherein a width of the second trench is greater than a width of the first trench, depositing a dielectric layer in the first trench and the second trench, wherein the dielectric layer partially fills the second trench, removing the dielectric layer in the second trench and forming a first gate region in the first trench and a second gate region in the second trench.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10141421
    Abstract: A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a region, and are electrically interconnected. The region between the first and the second gate electrodes overlaps the doped semiconductor region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 10109732
    Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 10103223
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 10090390
    Abstract: An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10050126
    Abstract: A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Chun-Wai Ng, Ruey-Hsin Liu
  • Patent number: 10038090
    Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Yu Chu, Chih-Chang Cheng, Tung-Yang Lin, Ruey-Hsin Liu
  • Publication number: 20180204924
    Abstract: A semiconductor device includes a substrate and a gate structure over a top surface of the substrate. The semiconductor device further includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well surrounds the source. The semiconductor device further includes a second well having a second dopant type opposite the first dopant type, wherein the second well surrounds the drain, an entirety of an upper most surface of the second well between the drain and the first well is coplanar with the top surface of the substrate, and the second well is spaced from the first well.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Chih-Chang CHENG, Fu-Yu CHU, Ruey-Hsin LIU