Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit on a semiconductor substrate. First and second gate electrode structures are disposed over the substrate and are spaced laterally from one another. A common source/drain region is disposed in the semiconductor substrate between the first and second gate electrode structures. An insulator layer overlies the first and second gate electrode structures. A source/drain contact extends through the insulator layer between the first and second gate electrode structures to contact the common source/drain region. First and second sidewall spacer structures are disposed along outer sidewalls of the first and second gate electrode structures, respectively, and have first and second outer sidewalls, respectively, adjacent to the source/drain contact.