Abstract: Josephson junctions are the main circuit element of superconducting quantum information devices due to their nonlinear inductance properties and fabrication scalability. However, large scale integration necessarily depends on high fidelity and high yielding fabrication of Josephson junctions. The standard Josephson junction technique depends on a submicron suspended resist Dolan bridge that tends to be very fragile and fractures during the fabrication process. The present invention is directed to a new tunnel junction resist mask that incorporates stress-relief channels to reduce the intrinsic stress of the resist, thereby increasing the survivability of the Dolan bridge during device processing, resulting in higher Josephson junction yield.

Abstract: The invention is directed to a device and method to engineer the superconducting transition width by suppressing the phonon populations responsible for the Cooper-pair decoherence below the superconducting transition temperature via phononic bandgap engineering. The device uses phononic crystals to engineer a phononic frequency gap that suppresses the decohering thermal phonon population just below the Cooper-frequency, and thus the normal conduction electron population. For example, such engineering can relax the cooling requirements for a variety of circuits yielding higher operational quality factors for superconducting electronics and interconnects.

Abstract: The invention is directed to a device and method to engineer the superconducting transition width by suppressing the phonon populations responsible for the Cooper-pair decoherence below the superconducting transition temperature via phononic bandgap engineering. The device uses phononic crystals to engineer a phononic frequency gap that suppresses the decohering thermal phonon population just below the Cooper-frequency, and thus the normal conduction electron population. For example, such engineering can relax the cooling requirements for a variety of circuits yielding higher operational quality factors for superconducting electronics and interconnects.

Abstract: The present invention relates to the use of gallium beam lithography to form superconductive structures. Generally, the method includes exposing a surface to gallium to form an implanted region and then removing material adjacent to and/or below that implanted region. In particular embodiments, the methods herein provide microstructures and nanostructures in any useful substrate, such as those including niobium, tantalum, tungsten, or titanium.

Abstract: A phase quantum bit is disclosed. In one embodiment, the phase quantum bit may comprise a Josephson junction and a distributed element coupled to the Josephson junction. The distributed element provides a capacitive component and an inductive component of the phase quantum bit.

Abstract: Systems and methods are provided for a hybrid qubit circuit assembly is provided. A first plural set of Josephson junctions is arranged in series on a first path between two nodes of a circuit. A second plural set of Josephson junctions is arranged in parallel with one another to form a direct current superconducting quantum interference device (DC SQUID). The DC SQUID is in parallel with the first plural set of Josephson junctions. A capacitor is in parallel with each of the first plural set of Josephson junctions and the DC SQUID.

Abstract: Systems and methods are provided for a hybrid qubit circuit assembly is provided. A first plural set of Josephson junctions is arranged in series on a first path between two nodes of a circuit. A second plural set of Josephson junctions is arranged in parallel with one another to form a direct current superconducting quantum interference device (DC SQUID). The DC SQUID is in parallel with the first plural set of Josephson junctions. A capacitor is in parallel with each of the first plural set of Josephson junctions and the DC SQUID.

Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.

Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.

Abstract: A phase quantum bit is disclosed. In one embodiment, the phase quantum bit may comprise a Josephson junction and a distributed element coupled to the Josephson junction. The distributed element provides a capacitive component and an inductive component of the phase quantum bit.