Patents by Inventor Ruqiang Bao

Ruqiang Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941282
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Publication number: 20180096900
    Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.
    Type: Application
    Filed: December 1, 2017
    Publication date: April 5, 2018
    Inventors: Ruqiang Bao, Siddarth A. Krishnan
  • Publication number: 20180090388
    Abstract: A method of forming a semiconductor device, includes forming a first work function metal and sacrificial layer on an n-type field effect transistor (nFET) and on a p-type field effect transistor (pFET), removing the sacrificial layer and the first work function metal from one of the nFET and the pFET, forming a second work function metal on the one of the nFET and the pFET, a thickness of the second work function metal being substantially the same as a thickness of the first work function metal, and removing the sacrificial layer from the other of the nFET and the pFET.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: Brent Alan ANDERSON, Ruqiang BAO, Paul Charles JAMISON, ChoongHyun LEE
  • Publication number: 20180090381
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Inventors: Ruqiang BAO, Dechao GUO, Vijay NARAYANAN
  • Publication number: 20180083015
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Application
    Filed: June 7, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Publication number: 20180083013
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Publication number: 20180082905
    Abstract: Semiconductor devices include one or more semiconductor fins. A gate is formed over the one or more semiconductor fins. A vertical sidewall is formed at a perimeter of the gate, the vertical sidewall having a uniform thickness along its height. A power rail is formed in contact with the vertical sidewall.
    Type: Application
    Filed: January 13, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Publication number: 20180083016
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Application
    Filed: October 19, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Publication number: 20180083017
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Publication number: 20180083120
    Abstract: Methods of forming a semiconductor device include laterally etching a dummy gate to recess the dummy gate underneath a spacer layer, such that the spacer layer overhangs the dummy gate. A sidewall of the dummy gate is nitridized. The dummy gate is etched away without removing the nitridized sidewall.
    Type: Application
    Filed: May 15, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Patent number: 9922884
    Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan
  • Patent number: 9922984
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Patent number: 9922983
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Patent number: 9917210
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Kangguo Cheng, Zheng Xu
  • Patent number: 9905476
    Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong
  • Patent number: 9899264
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Publication number: 20180047639
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 15, 2018
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Publication number: 20180047640
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 15, 2018
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Publication number: 20180026035
    Abstract: A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.
    Type: Application
    Filed: October 3, 2017
    Publication date: January 25, 2018
    Inventors: Ruqiang Bao, Unoh Kwon, Kai Zhao
  • Publication number: 20180006033
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Application
    Filed: April 28, 2017
    Publication date: January 4, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan