Patents by Inventor Russell B. Segal
Russell B. Segal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9754070Abstract: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.Type: GrantFiled: October 20, 2015Date of Patent: September 5, 2017Assignee: SYNOPSYS, INC.Inventor: Russell B. Segal
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Patent number: 9460258Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.Type: GrantFiled: December 26, 2013Date of Patent: October 4, 2016Assignee: SYNOPSYS, INC.Inventors: David L. Peart, Yan Lin, Aiguo Lu, Balkrishna R. Rashingkar, Russell B. Segal, Peiqing Zou
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Publication number: 20160042115Abstract: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Applicant: SYNOPSYS, INC.Inventor: Russell B. Segal
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Patent number: 9189591Abstract: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.Type: GrantFiled: October 23, 2014Date of Patent: November 17, 2015Assignee: SYNOPSYS, INC.Inventor: Russell B. Segal
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Patent number: 9026974Abstract: Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics.Type: GrantFiled: December 24, 2013Date of Patent: May 5, 2015Assignee: Synopsys, Inc.Inventors: Russell B. Segal, Balkrishna R. Rashingkar, Douglas Chang, Mattias A. Hembruch
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Publication number: 20150121328Abstract: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.Type: ApplicationFiled: October 23, 2014Publication date: April 30, 2015Inventor: Russell B. Segal
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Publication number: 20140181776Abstract: Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics.Type: ApplicationFiled: December 24, 2013Publication date: June 26, 2014Applicant: Synopsys, Inc.Inventors: Russell B. Segal, Balkrishna R. Rashingkar, Douglas Chang, Mattias A. Hembruch
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Publication number: 20140181773Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.Type: ApplicationFiled: December 26, 2013Publication date: June 26, 2014Applicant: Synopsys, Inc.Inventors: David L. Peart, Yan Lin, Aiguo Lu, Balkrishna R. Rashingkar, Russell B. Segal, Peiqing Zou
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Patent number: 6678644Abstract: Integrated circuit models having associated timing and tag information therewith for use with electronic design automation to effectively model timing exception information. The present invention includes a circuit block model which allows automated circuit optimization to be performed on extremely large circuits without the need to load all of the details of the circuit into computer memory. The circuit models of the present invention effectively model timing including timing exception information. The model of the present invention is associated with command information, e.g., textual commands, that describe tags (which model exceptions) and arrival and required times associated with the tags. Specifically, for the input pins of a circuit to be modeled, the present invention writes out a command defining each unique required tag associated with an input pin and also writes out commands associating each required tag with its input pin.Type: GrantFiled: September 13, 1999Date of Patent: January 13, 2004Assignee: Synopsys, Inc.Inventor: Russell B. Segal
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Patent number: 6496972Abstract: In a computer-implemented synthesis system, a method of optimizing a design of an integrated circuit device. The optimization process includes the computer-implemented steps of accessing a circuit netlist representing an integrated circuit design to be realized in physical form, wherein the circuit netlist includes a top-level block and at least a first and a second circuit block. The top-level block includes glue logic for coupling the first and second circuit blocks. The process creates a first model of the first circuit block and a second model of the second circuit block, the first model and the second model each operable for independently abstracting embodying circuitry of the first and second circuit blocks, respectively. The circuit netlist is optimized by independently optimizing the first circuit block and the second circuit block, and the top-level block to yield a fully optimized circuit netlist. The first and second circuit blocks are both independently optimized.Type: GrantFiled: September 13, 1999Date of Patent: December 17, 2002Assignee: Synopsys, Inc.Inventor: Russell B. Segal
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Patent number: 6438731Abstract: Integrated circuit models having associated timing and tag information therewith for use with design optimizations to effectively model timing exception information. The present invention includes a circuit block model which allows automated circuit optimization to be performed on extremely large circuits without the need to load all of the details of the circuit into computer memory. The circuit models of the present invention effectively model timing including timing exception information. The model of the present invention is associated with command information, e.g., textual commands, that describe tags (which model exceptions) and arrival and required times associated with the tags. Specifically, for the input pins of a circuit to be modeled, the present invention writes out a command defining each unique required tag associated with an input pin and also writes out commands associating each required tag with its input pin.Type: GrantFiled: September 13, 1999Date of Patent: August 20, 2002Assignee: Synopsys, Inc.Inventor: Russell B. Segal
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Patent number: 6317863Abstract: A method and apparatus for datapath placement of irregular logic, while still allowing control of wire lengths. The method and apparatus allow use of a objective, called a directed placement objective, that causes a logic gate to be placed at or near a coordinate, such as an input or output pin connected to the gate.Type: GrantFiled: September 30, 1997Date of Patent: November 13, 2001Assignee: Synopsys, Inc.Inventor: Russell B. Segal
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Patent number: 6023568Abstract: A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used for simulation or synthesis.Type: GrantFiled: November 15, 1996Date of Patent: February 8, 2000Assignee: Synopsys, Inc.Inventor: Russell B. Segal
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Patent number: 5953235Abstract: A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed.Type: GrantFiled: August 25, 1997Date of Patent: September 14, 1999Assignee: Synopsys, Inc.Inventors: Brent L. Gregory, Russell B. Segal
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Patent number: 5790830Abstract: A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used for simulation or synthesis.Type: GrantFiled: December 29, 1995Date of Patent: August 4, 1998Assignee: Synopsys, IncorporatedInventor: Russell B. Segal
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Patent number: 5748488Abstract: A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed.Type: GrantFiled: June 7, 1995Date of Patent: May 5, 1998Assignee: Synopsys, Inc.Inventors: Brent L. Gregory, Russell B. Segal
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Patent number: 5737574Abstract: A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed.Type: GrantFiled: June 7, 1995Date of Patent: April 7, 1998Assignee: Synopsys, IncInventors: Brent L. Gregory, Russell B. Segal
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Patent number: 5691911Abstract: A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed.Type: GrantFiled: June 6, 1995Date of Patent: November 25, 1997Assignee: Synopsys, Inc.Inventors: Brent L. Gregory, Russell B. Segal
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Patent number: 5680318Abstract: A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed.Type: GrantFiled: June 6, 1995Date of Patent: October 21, 1997Assignee: Synopsys Inc.Inventors: Brent L. Gregory, Russell B. Segal
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Patent number: 5661661Abstract: A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed.Type: GrantFiled: June 6, 1995Date of Patent: August 26, 1997Assignee: Synopsys, Inc.Inventors: Brent L. Gregory, Russell B. Segal