Abstract: Disclosed herein is a modular computing device that provides a user options to upgrade an existing computing device as improved expansion units become available without rendering the underlying base unit obsolete. The base unit of the modular computing device receives high-voltage AC power and one or more power supplies within the base unit converts the AC power to low-voltage DC power that is consumed within the base unit. An AC power transfer unit transfers AC power from the base unit to an expansion unit installed within an expansion dock of the base unit. One or more power supplies within the expansion unit convert the received AC power to low-voltage DC power that is consumed within the expansion unit.

Abstract: Disclosed herein is a modular computing device that provides a user options to upgrade an existing computing device as improved expansion units become available without rendering the underlying base unit obsolete. The base unit of the modular computing device receives high-voltage AC power and one or more power supplies within the base unit converts the AC power to low-voltage DC power that is consumed within the base unit. An AC power transfer unit transfers AC power from the base unit to an expansion unit installed within an expansion dock of the base unit. One or more power supplies within the expansion unit convert the received AC power to low-voltage DC power that is consumed within the expansion unit.

Abstract: Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.

Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.

Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory.

Abstract: Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.

Abstract: Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.

Abstract: Methods and apparatus are provided that may be utilized to maintain a copy of a processor cache directory on a remote device that may access data residing in a cache of the processor. Enhanced bus transactions containing cache coherency information used to maintain the remote cache directory may be automatically generated when the processor allocates or de-allocates cache lines. Rather than query the processor cache directory prior to each memory access to determine if the processor cache contains an updated copy of requested data, the remote device may query its remote copy.

Abstract: Methods, apparatus, and systems for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.

Abstract: Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. The remote device may include coherency logic, referred to herein as a snoop filter, designed to filter memory access requests that do not require bus commands to be sent to the processor. The snoop filter may filter requests based on a remote cache directory designed to mirror the processor cache directory, such that only those requests that target cache lines indicated to be valid in the processor cache result in snoop commands sent to the processor. Other requests (targeting data that is not cached in the processor) may be routed directly to memory without the latency conventionally associated with snoop requests.

Abstract: Methods and apparatus that may be utilized to reduce the amount of data related to encryption (hereinafter security metadata) that is accessible external to a device implementing the encryption, such as a system on a chip (SOC), are provided. The security metadata may be stored internal, for example in a secure random access memory (RAM) internal to the device, that is not accessible via external pins.

Abstract: Methods and devices that may be utilized in systems to dynamically update a security version parameter used to encrypt secure data are provided. The version may be maintained in persistent storage located on a device implementing the encryption, such as a system on a chip (SOC). The persistent storage does not require battery backing and, thus, the cost and complexity associated with conventional systems utilizing battery backed storage may be reduced.

Abstract: A computer system includes multiple caches and a cache line state directory structure, having at least a portion dedicated to a particular device cache within a particular device, and contains a fixed number of entries having a one-to-one correspondence to the cache lines of the cache to which it corresponds. The cache line state directory is used to determine whether it is necessary to send an invalidation message to the device cache. In the preferred embodiment, a dedicated portion of the cache line state directory structure corresponds to an I/O bridge device cache. Preferably, the cache line state directory also maintains state for one or more processor caches in a different format. The computer system preferably uses a NUMA architecture, the directories being maintained by node servers in each node.

Abstract: The present invention relates to methods of reducing proliferation of cells, enhancing apoptosis of cells or both in an individual in need thereof, comprising administering to the individual a combination of at least one farnesyl transferase inhibitor (FTI), such as an inhibitor of Ras function, and at least one signal transduction inhibitor (STI) in a therapeutically effective amount, wherein proliferation of cells is reduced and/or apoptosis of cells is enhanced in the individual. In one embodiment, the invention relates to a method of reducing proliferation of STI resistant cells, enhancing apoptosis of STI resistant cells, or both in an individual in need thereof, comprising administering to the individual a combination of at least one FTI and at least one STI in a therapeutically effective amount, wherein proliferation of STI resistant cells is reduced and/or apoptosis of STI resistant cells is enhanced in the individual. The present invention can be used to treat leukemia (e.g.