Patents by Inventor Ryo Fukuda

Ryo Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220128664
    Abstract: A laser radar includes: a base member; a drive part configured to rotate the base member about a rotation axis; and a plurality of optical units arranged on the base member at a predetermined interval in a circumferential direction about the rotation axis and each configured to project laser light in a direction away from the rotation axis. Here, projection directions of the laser lights from the plurality of optical units are different from each other in a direction parallel to the rotation axis.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Inventors: Yasuyuki KANO, Tetsuhisa HOSOKAWA, Ryo FUKUDA
  • Publication number: 20220093188
    Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.
    Type: Application
    Filed: March 16, 2021
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
  • Publication number: 20220093185
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.
    Type: Application
    Filed: March 16, 2021
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Masato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA
  • Patent number: 11277134
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: March 15, 2022
    Assignee: KlOXIA CORPORATION
    Inventors: Junya Matsuno, Kensuke Yamamoto, Ryo Fukuda, Masaru Koyanagi, Kenro Kubota, Masato Dome
  • Publication number: 20220059165
    Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.
    Type: Application
    Filed: May 25, 2021
    Publication date: February 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI, Kensuke YAMAMOTO, Masato DOME, Kei SHIRAISHI, Junya MATSUNO, Kenro KUBOTA
  • Patent number: 11232051
    Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: January 25, 2022
    Assignee: Kioxia Corporation
    Inventors: Kensuke Yamamoto, Masaru Koyanagi, Ryo Fukuda, Junya Matsuno, Kenro Kubota, Masato Dome
  • Publication number: 20210271615
    Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.
    Type: Application
    Filed: August 21, 2020
    Publication date: September 2, 2021
    Applicant: Kioxia Corporation
    Inventors: Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA, Masato DOME
  • Publication number: 20210226632
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.
    Type: Application
    Filed: August 26, 2020
    Publication date: July 22, 2021
    Applicant: Kioxia Corporation
    Inventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
  • Publication number: 20210177568
    Abstract: Provided is a seamless, cylindrical, high-density medical fabric which is thin and has high strength and low water permeability, the diameter of which can be reduced, which has high sewing strength in a region of at least 10 mm, in the lengthwise direction, from one end thereof, and to which damage can be minimized. The high-density medical fabric according to the present invention satisfies that: (1) both warps and wefts are synthetic fiber multifilament yarns having a total fineness of 60 dtex or lower; (2) the warps each have a single fiber fineness of 0.5 dtex or lower; (3) the cylindrical fabric has a two-wefts insertion woven structure in a region of at least 10 mm, in the lengthwise direction, from one end of the fabric; (4) the fabric has a cover factor of 1600-2400; and (5) the thickness of the fabric is 110 ?m or less.
    Type: Application
    Filed: November 7, 2018
    Publication date: June 17, 2021
    Applicant: Asahi Kasei Kabushiki Kaisha
    Inventors: Tokio Okuno, Ryo Fukuda
  • Patent number: 11004521
    Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 11, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Suematsu, Masaru Koyanagi, Kensuke Yamamoto, Ryo Fukuda
  • Publication number: 20210082525
    Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Yasuhiro SUEMATSU, Masaru KOYANAGI, Kensuke YAMAMOTO, Ryo FUKUDA
  • Publication number: 20210054545
    Abstract: Provided is a high-density medical fabric that can be suitably used as a graft for a branched stent graft, can accommodate diameter changes, has the burst strength required of a material to be implanted in a body, and has a seamless tubular shape that can narrow in diameter.
    Type: Application
    Filed: December 12, 2018
    Publication date: February 25, 2021
    Applicant: Asahi Kasei Kabushiki Kaisha
    Inventors: Tokio Okuno, Ryo Fukuda
  • Patent number: 9230653
    Abstract: According to an embodiment, a semiconductor device includes an IO terminal unit, an first IO line, and a second IO line. The IO terminal unit includes first and second IO terminals. The first IO line is electrically connected to one of both the first IO terminal and the second IO terminal. The second IO line is electrically connected to the other of both the first IO terminal and the second IO terminal. When the semiconductor device receives a first signal, the first IO terminal is electrically connected to the first IO line and the second IO terminal is electrically connected to the second IO line. When the semiconductor device receives a second signal, the first IO terminal is electrically connected to the second IO line and the second IO terminal is electrically connected to the first IO line. The second signal is different from the first signal.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: January 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Ryo Fukuda
  • Patent number: 9218882
    Abstract: A nonvolatile semiconductor memory device includes a first memory string including memory cell transistors and a first select transistor that are connected in series, a second memory string including memory cell transistors and a second select transistor that are connected in series, a bit line that is electrically connected to a first end of the first memory string and a first end of the second memory string, a first transistor having a gate that is connected to a second end of the first memory string, a source line that is electrically connected to a first end of the first transistor, and a second transistor having a gate that is connected to a second end of the second memory string, a first end that is electrically connected to a second end of the first transistor, and a second end that is electrically connected to the bit line.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Fukuda
  • Publication number: 20150262672
    Abstract: A nonvolatile semiconductor memory device includes a first memory string including memory cell transistors and a first select transistor that are connected in series, a second memory string including memory cell transistors and a second select transistor that are connected in series, a bit line that is electrically connected to a first end of the first memory string and a first end of the second memory string, a first transistor having a gate that is connected to a second end of the first memory string, a source line that is electrically connected to a first end of the first transistor, and a second transistor having a gate that is connected to a second end of the second memory string, a first end that is electrically connected to a second end of the first transistor, and a second end that is electrically connected to the bit line.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventor: Ryo FUKUDA
  • Publication number: 20150070990
    Abstract: According to an embodiment, a semiconductor device includes an IO terminal unit, an first IO line, and a second IO line. The IO terminal unit includes first and second IO terminals. The first IO line is electrically connected to one of both the first IO terminal and the second IO terminal. The second IO line is electrically connected to the other of both the first IO terminal and the second IO terminal. When the semiconductor device receives a first signal, the first IO terminal is electrically connected to the first IO line and the second IO terminal is electrically connected to the second IO line. When the semiconductor device receives a second signal, the first IO terminal is electrically connected to the second IO line and the second IO terminal is electrically connected to the first IO line. The second signal is different from the first signal.
    Type: Application
    Filed: March 12, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Ryo FUKUDA
  • Patent number: 8811079
    Abstract: A volatile memory area includes a plurality of second memory cells, a third select transistor, and a fourth select transistor. The plurality of second memory cells are electrically connected in series, and stacked above the substrate. The third select transistor is connected to one end of the plurality of second memory cells, and connected to a second bit line. The fourth select transistor is connected to the other end of the plurality of second memory cells, and unconnected to a second source line. A controller is configured to supply a first voltage to all gates of the second memory cells. The first voltage is capable of turning on the plurality of second memory cells.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryo Fukuda, Daisaburo Takashima
  • Patent number: 8736311
    Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryo Fukuda, Masaru Koyanagi
  • Patent number: D839836
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: February 5, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ryo Fukuda, Kazuhide Uriu, Kohei Masuda
  • Patent number: D865675
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 5, 2019
    Assignee: Panasonic Intellectual Property Management Co., Lt Ltd.
    Inventors: Ryo Fukuda, Kazuhide Uriu, Kohei Masuda