Abstract: A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.

Abstract: A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.

Abstract: This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

Abstract: A semiconductor memory device includes a sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second isolation transistor. The first node is connected to the first memory cell. The third node is connected to the second memory cell. A first amplification transistor and a second amplification transistor are connected between the first node and the third node. A third amplification transistor and a fourth amplification transistor are connected between the second node and the fourth node. This enables to parallelly execute read data transfer to the data lines and precharge to prepare for the next read operation.

Abstract: A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and drain layer and lower than the other of the potentials of the source and drain layer so that electric charges flow in the body region, and a potential of the second gate electrode is set to be higher as an absolute value than those of potentials of the source layer, drain layer, and first gate electrode so that electric charges flow from the body region, and in the data holding state, the memory cell is kept in a stationary state that a first amount of the electric charges flowing in the body region per unit time is substantially the same as a second amount of the electric charges flowing from the body region per unit time.

Abstract: A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.

Abstract: A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.

Abstract: This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

Abstract: A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.

Abstract: A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.

Abstract: The disclosure concerns a memory including a floating body provided in a semiconductor layer between a source and a drain and storing data; a first gate dielectric provided on a first surface of the body; a first gate electrode provided on the first surface via the first gate dielectric; a second gate dielectric provided on a second surface of the body different from the first surface; a second gate electrode provided on the second surface via the second gate dielectric; a driver driving the first gate electrode and the second gate electrode; and a sense amplifier writing into the memory cells first data showing a sate of a small charge amount in a state that a voltage of the second gate electrode at a data writing time is brought closer to a potential of the source layer than a voltage of the second gate electrode at a data holding time.

Abstract: This disclosure concerns a memory including a memory cell including a drain, a source and a floating body, wherein when a refresh operation is executed, a first current is carried from the drain or the source to the body and a second current is carried from the body to the second gate electrode by applying a first voltage and a second voltage to the first gate electrode and the second gate electrode, the first voltage and the second voltage being opposite in polarity to each other, and a state of the memory cell is covered to an stationary state in which an amount of the electric charges based on the first current flowing in one cycle of the refresh operation is almost equal to an amount of the electric charges based on the second current flowing in one cycle of the refresh operation.

Abstract: A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.

Abstract: This disclosure concerns a semiconductor memory comprising memory cells; word lines connected to gates of the cells; n bit lines connected to the memory cells; sense amplifiers connected to the bit lines; refresh cells provided to correspond to the word lines, respectively, and provided to correspond to k bit lines, where k is a natural number smaller than n, one of the refresh cells storing therein refresh data indicating whether to perform a refresh operation on k memory cells out of the plural memory cells connected to a corresponding word line out of the plural word lines and connected to the k bit lines, respectively; a refresh sense amplifier reading the refresh data; and a refresh selection part provided to correspond to the refresh sense amplifier, and selecting whether to perform the refresh operation on the k memory cells according to the refresh data read by the refresh sense amplifier.

Abstract: This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.

Abstract: A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.

Abstract: This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

Abstract: The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.

Abstract: A semiconductor memory device comprises a memory core, data control circuit, flag register, data register and computation circuit. The memory core has a plurality of memory cells for storing data. The data control circuit writes and reads first test data to and from the memory cells in synchrony with a clock signal. The flag register stores a plurality of flag data items. The data register stores second test data input corresponding to input of a command. The computation circuit performs, at every cycle, computation of the second test data, stored in the data register, and each of the flag data items stored in the flag register, thereby generating the first test data, until an n-th (n is a positive integer) cycle of the clock signal is reached. The first test data is written to the memory cells by the data control circuit.

Abstract: A memory cell array includes a plurality of memory cells arranged at intersections of bitline pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.