Patents by Inventor Ryo Haruta

Ryo Haruta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200099635
    Abstract: A control apparatus includes an execution controller configured to, when information related to an instruction for causing an information processing apparatus to execute a specific process is posted by a user in a talk room in which each of plural participating users is capable of posting and viewing information, control one information processing apparatus among information processing apparatuses associated with other users, among the users participating in the talk room, than the user who posts the information, to execute the specific process.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 26, 2020
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Ryoto YABUSAKI, Kiyoshi YASUKAWA, Tsuyoshi TODA, Satoshi MARUYAMA, Takafumi HARUTA, Yohei MAKINO, Ryo MATSUMOTO
  • Publication number: 20200097221
    Abstract: A control apparatus includes a receiving unit and a controller. The receiving unit receives an execution command for a predetermined process in a service. The service displays a post posted by a user in a chronological order in a predetermined direction and is usable for commanding execution of the process. The controller performs control to perform carousel-layout display such that, if the post corresponding to the execution command for the process received by the receiving unit includes multiple posts, the multiple posts and command information related to the execution command for the process corresponding to the multiple posts are displayed in the service in a slidably-operable manner in a direction intersecting the predetermined direction.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 26, 2020
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Ryo MATSUMOTO, Kiyoshi YASUKAWA, Yohei MAKINO, Tsuyoshi TODA, Satoshi MARUYAMA, Takafumi HARUTA, Ryoto YABUSAKI, Yu MISHIMA
  • Publication number: 20200099643
    Abstract: A control device includes a control unit that performs control to execute specific processing associated with first conditions in a case where information posted by a user satisfies the first conditions in an individual chat in which one user and a chatbot participate and that performs control not to execute the specific processing in a case where only the first conditions are satisfied and to execute the specific processing in a case where second conditions different from the first conditions are satisfied in a group chat in which plural users and a chatbot participate.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 26, 2020
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Yohei MAKINO, Tsuyoshi TODA, Kiyoshi YASUKAWA, Satoshi MARUYAMA, Ryoto YABUSAKI, Ryo MATSUMOTO, Takafumi HARUTA
  • Publication number: 20080122050
    Abstract: A power semiconductor device in which a semiconductor element is die-mount-connected onto a lead frame in a Pb-free manner. In a die-mount-connection with a large difference of thermal expansion coefficient between a semiconductor element 1 and a lead frame 2, the connection is made with an intermetallic compound 200 having a melting point of 260° C. or higher or a Pb-free solder having a melting point of 260° C. or higher to 400° C. or lower, at the same time, the thermal stress produced in temperature cycles is buffered by a metal layer 100 having a melting point of 260° C. or higher. A Pb-free die-mount-connection which does not melt at the time of reflowing but have no chip crack to occur according to thermal stress can be achieved.
    Type: Application
    Filed: June 15, 2005
    Publication date: May 29, 2008
    Inventors: Osamu Ikeda, Masahide Okamoto, Ryo Haruta, Hidemasa Kagii, Hiroi Oka, Hiroyuki Nakamura
  • Patent number: 6897570
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: May 24, 2005
    Assignee: Renesas Technology, Corporation
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Patent number: 6887739
    Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: May 3, 2005
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6844219
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: January 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
  • Patent number: 6764878
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: July 20, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6759279
    Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: July 6, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Publication number: 20040005733
    Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Application
    Filed: July 3, 2003
    Publication date: January 8, 2004
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Publication number: 20030230809
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Application
    Filed: January 9, 2003
    Publication date: December 18, 2003
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Patent number: 6621160
    Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: September 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo
  • Patent number: 6590275
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: July 8, 2003
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6563212
    Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: May 13, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo
  • Patent number: 6512176
    Abstract: In a ball grid array type semiconductor device mounted on a printed wiring board, the external terminals can be prevented from being broken down even when the ambient temperature on the device is repeatedly changed. A flexible adhesive member for gluing the semiconductor chip to an insulating tape is provided to cover up to a region including the lands to which the external terminals are bonded and which are provided on the insulating tape surface. The flexible adhesive member for covering the lands may be replaced by a flexible low-elasticity member.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: January 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Yaguchi, Ryo Haruta, Masahiro Ichitani
  • Publication number: 20020192872
    Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Application
    Filed: August 8, 2002
    Publication date: December 19, 2002
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Publication number: 20020182776
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Application
    Filed: July 12, 2002
    Publication date: December 5, 2002
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6476466
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: November 5, 2002
    Assignee: Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6476467
    Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: November 5, 2002
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems Ltd.
    Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
  • Patent number: 6465876
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bond ed to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki